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參數(shù)資料
| 型號： | ORT82G5-3FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 26/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
14
Figure 2. Top Level Block Diagram, Embedded Core Logic (Channel AC)
The Embedded Core provides transceiver functionality for four or eight serial data channels and is organized into
two blocks, each supporting two or four channels. Each channel is identied by both a block identier [A:B] and a
channel identier [A:D]. In the ORT42G5 only the channel identiers C and D are used. (This naming convention
follows that of the ORT82G5).
The data channels can operate independently or they can be combined together (aligned) to achieve higher bit
rates. The mode operation of the core is dened by a set of control registers, which can be written through the sys-
tem bus interface. Also, the status of the core is stored in a set of status registers, which can be read through the
system bus interface.
The transmitter section for each channel accepts 40 bits of data or 32 bits of data and eight control/status bits from
the FPGA logic and optionally encodes the data using 8b/10b encoding. It also accepts the low-speed reference
clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The data is
then serialized and the serialized data are available at the differential CML output terminated in 86 Ω to drive either
an optical transmitter or coaxial media or circuit board/backplane.
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. The retimed data are also deseri-
alized and optionally 8b/10b decoded. The receiver also optionally recognizes the comma characters or code viola-
tions and aligns the bit stream to the proper word boundary. The resulting parallel data is optionally passed to the
multi-channel alignment block before it is presented to the FPGA logic.
8b/10b Encoding and Decoding
In 8b/10b mode, the FPGA logic will receive/transmit 32 bits of data and 4 K_CTRL bits from/to the embedded
core. In the transmit direction, four additional input bits force a negative disparity present state. The embedded core
logic will encode the data to or decode the data from a 10-bit format according to the FC-PH ANSI X3.230:1994
standard (which is also the encoding used by the IEEE 802.3ae Ethernet standard). This encoding/decoding
scheme also allows for the transmission of special characters and supports error detection.
Common Logic, Block A
Next Channel
.
..
Last Channel (BD)
Backplane
Serial
Links
Receive Channel AC
2:1 MUX
(x40)
DEMUX
Block
Link State
Machine
RX SER-
DES Block
Multi -
Channel
Alignment
Block
TX SERDES
Block
Interface and
MUX Block
Transmit Channel AC
RCK78A
TCK78A
MRWDAC[39:0]
CV_SELAC
RWCKAC
RSYS_CLK_A2
TSYS_CLK_AC
TWDAC[31:0]
TCOMMAC[3:0]
.
FPGA
Logic
HDOUT[P:N]_AC
2
HDIN[P:N]_AC
REFCLK[P:N]_A
2
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相關(guān)代理商/技術(shù)參數(shù) |
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| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORT82G5 ispGDX256 is pPAC PwrMgr 1208 BC RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
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