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參數(shù)資料
| 型號： | ORT82G5-3FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 52/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
38
data rate and bit-width so the FPGA core can run at 1/4th this frequency which gives a range of 15 to 92.5 MHz for
the data in and out of the FPGA.
Internal Clock Signals at the FPGA/Core Interface for the ORT42G5
There are several clock signals dened at the FPGA/Embedded Core interface in addition to the external reference
clock for each SERDES block. All of the ORT42G5 clock signals are shown in Figure 17 and are described follow-
ing the gure.
Figure 17. ORT42G5 Clock Signals (High Speed Serial I/O Also Shown)
REFCLKP_[A:B], REFCLKN_[A:B]:
These are the differential reference clocks provided to the ORT42G5 device as described earlier. They are used as
the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbps, the reference clocks
will be at a frequency of 156.25 MHz.
RWCK[AC, AD, BC, BD]:
These are the low-speed receive clocks from the embedded core to the FPGA across the core-FPGA interface.
These are derived from the recovered low-speed complementary clocks from the SERDES blocks. RWCKAC
belongs to Channel AC, RWCKBC belongs to channel BC and so on. With a reference clock input of 156.25 MHz,
these clocks operate at 78.125 MHz.
RCK78[A:B]:
These are muxed outputs of RWCKA[C or D] and RWCKB[C or D] respectively. With a reference clock input of
156.25 MHz, these clocks operate at 78.125 MHz.
RSYS_CLK_[A:B]2
These clocks are inputs to the SERDES blocks A and B respectively from the FPGA. These are used by each
channel as the read clock to read received data from the alignment FIFO within the embedded core. Clock
RSYS_CLK_A2 is used by channels in the SERDES block A and RSYS_CLK_B2 by channels in the SERDES
block B. To guarantee that there is no overow in the alignment FIFO, it is an absolute requirement that the write
and read clocks be frequency locked within 0 ppm. Examples of how to achieve this are shown in the later section
on recommended board-level clocking.
FPGA
Logic
Common Logic, Block A
Channel AC
Channel AD
RCK78A
TCK78A
RSYS_CLK_A2
TSYS_CLK_AC
RWCKAC
TSYS_CLK_AD
REFCLK[P:N]_A
2
HDIN[P:N]_AD
HDOUT[P:N]_AD
2
HDOUT[P:N]_AC
2
HDIN[P:N]_AC
2
TCK78A
Backplane
Serial
Link
Common Logic, Block B
Channel BC
Channel BD
RCK78B
TCK78B
RSYS_CLK_B2
TSYS_CLK_BC
RWCKBC
RWCKBD
TSYS_CLK_BD
REFCLK[P:N]_B
2
HDIN[P:N]_BD
HDOUT[P:N]_BD
2
HDOUT[P:N]_BC
2
HDIN[P:N]_BC
2
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| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORT82G5 ispGDX256 is pPAC PwrMgr 1208 BC RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
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