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參數(shù)資料
| 型號： | ORT82G5-3FN680C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 66/119頁 |
| 文件大小： | 0K |
| 描述： | IC TRANCEIVERS FPSC 680FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
50
Start Up Sequence for the ORT42G5
The following sequence is required by the ORT42G5 device. For information required for simulation that may be dif-
ferent than this sequence, see the ORT42G5 Design Kit.
1.
Initiate a hardware reset by making PASB_RESETN low. Keep this low during FPGA conguration of the
device. The device will be ready for operation 3 ms after the low to high transition of PASB_RESETN.
2.
At startup, the legacy SERDES channel logic must be powered down and removed from any multi-channel
alignment groups:
Setting bit 1 to one in registers at locations 30002, 30012, 30102, 30112, 30003, 30013, 30103 and 30113
powers down the legacy logic. (Note that the reset value for these bits is 0.)
Setting bits 4 and 5 to zero (reset condition) in the register at locations 30810 and 30910 removes the legacy
logic from any alignment group.
3.
Congure the following SERDES internal and external registers. Note that after device initialization, all alarm
and status bits should be read once to clear them. A subsequent read will provide the valid state.
Set the following bits in register 30800:
– Bits LCKREFN_[AC and AD] to 1, which implies lock to data.
– Bits ENBYSYNC_[AC and AD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30801:
– Bits LOOPENB_[AC and AD] to 1 if high-speed serial loopback is desired.
Set the following bits in register 30900:
– Bits LCKREFN_[BC and BD] to 1 which implies lock to data.
– Bits ENBYSYNC_[BC and BD] to 1 which enables dynamic alignment to comma.
Set the following bits in register 30901:
– Bits LOOPENB_[BC and BD] to 1 if high-speed serial loopback is desired.
Set the following bits in registers 30022, 30032, 30122, 30132:
– TXHR set to 1 if TX half-rate is desired.
– 8b10bT set to 1 if 8b10b encoding is desired.
Set the following bits in registers 30023, 30033, 30123, 30133:
– RXHR Set to 1 if RX half-rate is desired.
– 8b10bR set to 1 if 8b10b decoding is desired.
– LINKSM set to 1 if the Fibre Channel state machine is desired.
Assert GSWRST bit by writing 1’s to both SERDES blocks. Deassert GSWRST bit by writing 0’s to both SER-
DES blocks. Wait 3 ms. If higher speed serial loopback has been selected, the receive PLLs will use this time
to lock to the new serial data.
Monitor the following alarm bits in registers 30020, 30030, 30120, 30130:
– LKI, PLL lock indicator. 1 indicates that PLL has achieved lock.
4.
If 8b/10b mode is enabled, enable link synchronization by periodically sending the following sequence three
times:
– K28.5 D21.4 D21.5 D21.5 or any other idle ordered set (starting with a /comma/) in FC mode.
– /comma/ characters for the XAUI state machine and /A/ characters for word and channel alignment in XAUI
mode.
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| ORT82G5-3FN680C1 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT82G5-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Ev Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT82G5-G2-PAC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORT82G5 ispGDX256 is pPAC PwrMgr 1208 BC RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
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