參數(shù)資料
型號: P60ARM-IG
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數(shù): 3/120頁
文件大?。?/td> 1275K
代理商: P60ARM-IG
iii
Table of Contents
1.0
Introduction
1.1
1.2
Signal Description
Programmer's Model
3.1
Hardware Configuration
3.2
Operating Mode Selection
3.3
Registers
3.4
Exceptions
3.5
Reset
Instruction Set
4.1
Instruction Set Summary
4.2
The Condition Field
4.3
Branch and Branch with link (B, BL)
4.4
Data processing
4.5
PSR Transfer (MRS, MSR)
4.6
Multiply and Multiply-Accumulate (MUL, MLA)
4.7
Single data transfer (LDR, STR)
4.8
Block data transfer (LDM, STM)
4.9
Single data swap (SWP)
4.10
Software interrupt (SWI)
4.11
Coprocessor data operations (CDP)
4.12
Coprocessor data transfers (LDC, STC)
4.13
Coprocessor register transfers (MRC, MCR)
4.14
Undefined instruction
4.15
Instruction Set Examples
Memory Interface
5.1
Cycle types
5.2
Byte addressing
5.3
Address timing
5.4
Memory management
5.5
Locked operations
5.6
Stretching access times
Coprocessor Interface
6.1
Interface signals
6.2
Data transfer cycles
6.3
Register transfer cycle
6.4
Privileged instructions
6.5
Idempotency
6.6
Undefined instructions
Instruction Cycle Operations
7.1
Branch and branch with link
7.2
Data Operations
7.3
Multiply and multiply accumulate
7.4
Load register
7.5
Store register
1
2
3
5
9
9
9
ARM60 Block diagram
ARM60 Functional Diagram
2.0
3.0
10
13
17
19
19
20
21
23
30
34
36
41
48
50
52
54
57
59
60
65
65
66
68
68
69
69
71
71
72
72
72
72
73
75
75
75
77
77
78
4.0
5.0
6.0
7.0
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