參數(shù)資料
型號: P60ARM-IG
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數(shù): 71/120頁
文件大小: 1275K
代理商: P60ARM-IG
Memory Interface
67
Figure 30: Memory Cycle Optimization
If a byte write is requested (STRB), ARM60
at each byte location within the word. The memory system must decode
addressed byte.
will broadcast the byte value across the data bus, presenting it
A[1:0]
to enable writing only to the
One way of implementing the byte decode in a DRAM system is to separate the 32 bit wide block of DRAM
into four byte wide banks, and generate the column address strobes independently as shown in
Decoding Byte Accesses to Memory
.
Figure 31:
When the processor is configured for Little Endian operation byte 0 of the memory system should be
connected to data lines 7 through 0 (
D[7:0]
) and strobed by
data lines 15 though 8, and so on. This has the added advantage of reducing the load on each column strobe
driver, which improves the precision of this time critical signal.
nCAS0
.
nCAS1
drives the bank connected to
In the Big Endian case, byte 0 of the memory system should be connected to data lines 31 through 24
.
MCLK
A[31:0]
nMREQ
SEQ
nCAS
I-cycle
S-cycle
nRAS
D[31:0]
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