參數(shù)資料
型號: P60ARM-IG
廠商: Zarlink Semiconductor Inc.
英文描述: Low power, general purpose 32-bit RISC microprocessor
中文描述: 低功耗,通用32位RISC微處理器
文件頁數(shù): 37/120頁
文件大?。?/td> 1275K
代理商: P60ARM-IG
Instruction Set - MRS, MSR
33
(4)
MSR - transfer immediate value to PSR flag bits only
MSR{cond} <psrf>,<#expression>
The expression should symbolise a 32 bit value of which the most significant four bits are written
to the N,Z,C & V flags respectively.
{cond} - two-character condition mnemonic, see
Figure 6: Condition Codes
Rd and Rm are expressions evaluating to a register number other than R15
<psr> is CPSR, CPSR_all, SPSR or SPSR_all. (CPSR and CPSR_all are synonyms as are SPSR and SPSR_all)
<psrf> is CPSR_flg or SPSR_flg
Where <#expression> is used, the assembler will attempt to generate a shifted immediate 8-bit field to
match the expression. If this is impossible, it will give an error.
4.5.5 Examples
In User mode the instructions behave as follows:
MSR
MSR
CPSR_all,Rm
CPSR_flg,Rm
; CPSR[31:28] <- Rm[31:28]
; CPSR[31:28] <- Rm[31:28]
MSR
CPSR_flg,#0xA0000000 ; CPSR[31:28] <- 0xA
; (i.e. set N,C; clear Z,V)
MRS
Rd,CPSR
; Rd[31:0] <- CPSR[31:0]
In privileged modes the instructions behave as follows:
MSR
CPSR_all,Rm
MSR
CPSR_flg,Rm
; CPSR[31:0] <- Rm[31:0]
; CPSR[31:28] <- Rm[31:28]
MSR
CPSR_flg,#0x50000000 ; CPSR[31:28] <- 0x5
; (i.e. set Z,V; clear N,C)
MRS
Rd,CPSR
; Rd[31:0] <- CPSR[31:0]
MSR
MSR
SPSR_all,Rm
SPSR_flg,Rm
; SPSR_<mode>[31:0] <- Rm[31:0]
; SPSR_<mode>[31:28] <- Rm[31:28]
MSR
SPSR_flg,#0xC0000000 ; SPSR_<mode>[31:28] <- 0xC
; (i.e. set N,Z; clear C,V)
MRS
Rd,SPSR
; Rd[31:0] <- SPSR_<mode>[31:0]
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