參數(shù)資料
型號(hào)： P60ARM-IG
廠商： Zarlink Semiconductor Inc.
英文描述： Low power, general purpose 32-bit RISC microprocessor
中文描述： 低功耗，通用32位RISC微處理器
文件頁數(shù)： 61/120頁
文件大?。?/td> 1275K
代理商： P60ARM-IG
Instruction Set - MRC, MCR
57
4.13 Coprocessor register transfers (MRC, MCR)
The is only executed if the condition is true. The various conditions are defined at the beginning of this
chapter. The instruction encoding is shown in
Figure 27: Coprocessor Register Transfer Instructions
.
This class of instruction is used to communicate information directly between ARM60 and a coprocessor.
An example of a coprocessor to ARM60 register transfer (MRC) instruction would be a FIX of a floating
point value held in a coprocessor, where the floating point number is converted into a 32 bit integer within
the coprocessor, and the result is then transferred to an ARM60 register. A FLOAT of a 32 bit value in an
ARM60 register into a floating point value within the coprocessor illustrates the use of an ARM60 register
to coprocessor transfer (MCR).
Figure 27: Coprocessor Register Transfer Instructions
An important use of this instruction is to communicate control information directly from the coprocessor
into the ARM60 CPSR flags. As an example, the result of a comparison of two floating point values within
a coprocessor can be moved to the CPSR to control the subsequent flow of execution.
Note for future compatbility the ARM610 has an internal coprocessor (#15) for control of on-chip functions.
Accesses to this coprocessor are performed during coprocessor register transfers.
4.13.1 The Coprocessor Telds
The CP# field is used, as for all coprocessor instructions, to specify which coprocessor is being called upon.
The CP Opc, CRn, CP and CRm fields are used only by the coprocessor, and the interpretation presented
here is derived from convention only. Other interpretations are allowed where the coprocessor
functionality is incompatible with this one. The conventional interpretation is that the CP Opc and CP fields
21
Cond
0
11
12
15
16
19
20
24
27
28
31
23
CP#
7
8
1110
CRn
CP
CRm
5
4
3
1
L
CP Opc
Rd
Coprocessor number
ARM source/destination register
Coprocessor source/destination register
Coprocessor information
Coprocessor operand register
Coprocessor operation mode
Condition field
Load/Store bit
0 = Store to Co-Processor
1 = Load from Co-Processor
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