參數(shù)資料
型號： P610ARM-KW
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 140/173頁
文件大小： 897K
代理商： P610ARM-KW
Boundary-Scan Test Interface
ARM610 Data Sheet
11-6
In the SHIFT-DR state, the previously captured test data is shifted out of the BS
register via the
TDO
pin, while new test data is shifted in via the
register parallel input latch. In the UPDATE-DR state, the new test data is transferred
into the BS register parallel output latch. This data is applied immediately to the system
logic and system pins. The first INTEST vector should be clocked into the boundary-
scan register, using the SAMPLE/PRELOAD instruction, prior to selecting INTEST to
ensure that known data is applied to the system logic.
TDI
pin to the BS
Single-step operation is possible using the INTEST instruction.
11.6.7 IDCODE (1110)
The IDCODE instruction connects the device identification register (or ID register)
between
TDI
and
TDO
. The ID register is a 32-bit register that allows the manufacturer,
part number and version of a component to be determined through the TAP.
When the instruction register is loaded with the IDCODE instruction, all the boundary-
scan cells are placed in their normal (system) mode of operation.
In the CAPTURE-DR state, the device identification code (specified at the end of this
section) is captured by the ID register. In the SHIFT-DR state, the previously captured
device identification code is shifted out of the ID register via the
shifted in via the
TDI
pin into the ID register. In the UPDATE-DR state, the ID register
is unaffected.
TDO
pin, while data is
11.6.8 BYPASS (1111)
The BYPASS instruction connects a 1–bit shift register (the BYPASS register) between
TDI
and
TDO
.
When the BYPASS instruction is loaded into the instruction register, all the boundary-
scan cells are placed in their normal (system) mode of operation. This instruction has
no effect on the system pins.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-
DR state, test data is shifted into the bypass register via
delay of one
TCK
cycle. The first bit shifted out will be a zero. The bypass register is
not affected in the UPDATE-DR state.
TDI
and out via
TDO
after a
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