參數(shù)資料
型號： P610ARM-KW
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 56/173頁
文件大?。?/td> 897K
代理商： P610ARM-KW
Instruction Set - LDR, STR
ARM610 Data Sheet
4-28
O
4.7.8 Assembler syntax
<LDR|STR>{cond}{B}{T} Rd,<Address>
where:
LDR
load from memory into a register
STR
store from a register into memory
{cond}
two-character condition mnemonic. See
·
Table 4-2: Condition code
summaryon page 4-6.
{B}
if B is present then byte transfer, otherwise word transfer
{T}
if T is present the W bit will be set in a post-indexed instruction, forcing
non-privileged mode for the transfer cycle. T is not allowed when a
pre-indexed addressing mode is specified or implied.
Rd
is an expression evaluating to a valid register number.
Rn and Rm are expressions evaluating to a register number. If Rn is R15 then the
assembler will subtract 8 from the offset value to allow for ARM610
pipelining. In this case base write-back should not be specified.
<Address> can be:
1
An expression which generates an address:
<expression>
The assembler will attempt to generate an instruction using
the PC as a base and a corrected immediate offset to
address the location given by evaluating the expression. This
will be a PC relative, pre-indexed address. If the address is
out of range, an error will be generated.
2
A pre-indexed addressing specification:
[Rn]
offset of zero
[Rn,<#expression>]{!}
offset of <expression>
bytes
[Rn,{+/-}Rm{,<shift>}]{!}
offset of +/- contents of
index register, shifted
by <shift>
3
A post-indexed addressing specification:
[Rn],<#expression>
offset of <expression>
bytes
[Rn],{+/-}Rm{,<shift>}
offset of +/- contents of
index register, shifted
as by <shift>
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