參數(shù)資料
型號： P610ARM-KW
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 96/173頁
文件大小： 897K
代理商： P610ARM-KW
Instruction and Data Cache (IDC)
ARM610 Data Sheet
6-2
6.1
Introduction
ARM610 contains a 4kByte mixed instruction and data cache. The IDC has 256 lines
of 16 bytes (four words), organised as a 64-way set-associative cache, and uses the
virtual addresses generated by the processor core. The IDC is always reloaded a line
at a time (four words). It may be enabled or disabled via the ARM610 Control Register
and is disabled on
nRESET
. The operation of the cache is further controlled by two
bits:
Cacheable
and
Updateable
, which are stored in the Memory Management Page
Tables (see
·
Chapter 9, Memory Management Unit
the IDC, the MMU must be enabled. The two functions may however be enabled
simultaneously, with a single write to the Control Register.
). For this reason, in order to use
6.2
Cacheable Bit - C
The
used for subsequent read operations. Typically main memory will be marked as
Cacheable to improve system performance, and I/O space as Non-cacheable to stop
the data being stored in ARM610's cache. For example if the processor is polling a
hardware flag in I/O space, it is important that the processor is forced to read data from
the external peripheral, and not a copy of initial data held in the cache. The
bit can be configured for both pages and sections.
Cacheable
bit determines whether data being read may be placed in the IDC and
Cacheable
6.3
Updateable Bit - U
The
during a write operation to maintain consistency with the external memory. In certain
cases automatic updating of cached data is not required: for instance, when using the
MEMC1a memory manager, a read operation in the address space between
3400000H -3FFFFFFH would access the ROMs, but a write operation in the same
address space would change a MEMC register, and should not affect the cached ROM
data. The
Updateable
bit can only be configured by the Level One descriptor: that is
an entire section or all the pages for a single Level One descriptor share the same
configuration.
Updateable
bit determines whether the data in the cache should be updated
6.4
IDC Operation
When the processor performs a read or write operation, the translation entry for that
address is inspected and the state of the cacheable and updateable bits determines
the subsequent action.
6.4.1 Cacheable reads C = 1
The cache is searched for the relevant data; if found in the cache, the data is fed to the
processor using a fast clock cycle (from
FCLK
an external memory access is initiated to read the appropriate line of data (four words)
from external memory and it is stored in a pseudo-randomly chosen entry in the cache
(a linefetch operation).
). If the data is not found in the cache,
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