參數(shù)資料
型號： P610ARM-KW
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 85/173頁
文件大?。?/td> 897K
代理商： P610ARM-KW
Instruction Set - Examples
ARM610 Data Sheet
4-57
O
Div2
CMP
SUBCS Ra,Ra,Rb
ADDCS Rc,Rc,Rcnt
MOVS
Rcnt,Rcnt,LSR#1
MOVNE Rb,Rb,LSR#1
BNE
Div2
Ra,Rb
; Test for possible subtraction.
; Subtract if ok,
; put relevant bit into result
; shift control bit
; halve unless finished.
;
; Divide result in Rc,
; remainder in Ra.
Overflow detection in the ARM610
1
Overflow in unsigned multiply with a 32-bit result
UMULL
Rd,Rt,Rm,Rn
TEQ
Rt,#0
BNE
overflow
;3 to 6 cycles
;+1 cycle and a register
2
Overflow in signed multiply with a 32-bit result
SMULL
Rd,Rt,Rm,Rn
TEQ
Rt,Rd ASR#31
BNE
overflow
;3 to 6 cycles
;+1 cycle and a register
3
Overflow in unsigned multiply accumulate with a 32-bit result
UMLAL
Rd,Rt,Rm,Rn
TEQ
Rt,#0
BNE
overflow
;4 to 7 cycles
;+1 cycle and a register
4
Overflow in signed multiply accumulate with a 32-bit result
SMLAL
Rd,Rt,Rm,Rn
TEQ
Rt,Rd, ASR#31
BNE
overflow
;4 to 7 cycles
;+1 cycle and a register
5
Overflow in unsigned multiply accumulate with a 64-bit result
UMULL
Rl,Rh,Rm,Rn
ADDS
Rl,Rl,Ra1
ADC
Rh,Rh,Ra2
BCS
overflow
;3 to 6 cycles
;lower accumulate
;upper accumulate
;1 cycle and 2 registers
6
Overflow in signed multiply accumulate with a 64-bit result
SMULL
Rl,Rh,Rm,Rn
ADDS
Rl,Rl,Ra1
ADC
Rh,Rh,Ra2
BVS
overflow
;3 to 6 cycles
;lower accumulate
;upper accumulate
;1 cycle and 2 registers
Note
Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit
result, since overflow does not occur in such calculations.
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