參數(shù)資料
型號： P610ARM-KW
廠商： Zarlink Semiconductor Inc.
英文描述： General purpose 32-bit microprocessor
中文描述： 通用32位微處理器
文件頁數(shù)： 79/173頁
文件大?。?/td> 897K
代理商： P610ARM-KW
Instruction Set - LDC, STC
ARM610 Data Sheet
4-51
O
4.13.7 Assembler syntax
<LDC|STC>{cond}{L} p#,cd,<Address>
LDC
load from memory to coprocessor
STC
store from coprocessor to memory
{L}
when present perform long transfer (N=1), otherwise perform short
transfer (N=0)
{cond}
two character condition mnemonic. See
·
Table 4-2: Condition code
summaryon page 4-6.
p#
the unique number of the required coprocessor
cd
is an expression evaluating to a valid coprocessor register number
that is placed in the CRd field
<Address> can be:
1
An expression which generates an address:
<expression>
The assembler will attempt to generate an instruction using
the PC as a base and a corrected immediate offset to
address the location given by evaluating the expression. This
will be a PC relative, pre-indexed address. If the address is
out of range, an error will be generated.
2
A pre-indexed addressing specification:
[Rn]
offset of zero
[Rn,<#expression>]{!}
offset of <expression> bytes
3
A post-indexed addressing specification:
[Rn],<#expression>
offset of <expression> bytes
{!}
write back the base register
(set the W bit) if! is present
Rn
is an expression evaluating
to a valid ARM610 register
number.
Note
If Rn is R15, the assembler will subtract 8 from the offset value to allow for ARM610
pipelining.
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