參數資料
型號: PC755
廠商: Atmel Corp.
英文描述: PowerPC 755/745 RISC Microprocessor
中文描述: RISC微處理器PowerPC的745分之755
文件頁數: 17/50頁
文件大?。?/td> 1064K
代理商: PC755
17
PC755/745
2138D–HIREL–06/03
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1) with the calculated case temperature. The actual value of R
éy
JC
for the part is less than 0.1
°
C/W.
R
efer to Section “Thermal Management Information“ page 19 for more details about thermal management.
Note:
Package Thermal
Characteristics for HiTCE
Table 7 provides the package thermal characteristics for the PC755, HiTCE.
Notes:
1. Simulation, no convection air flow.
2. Per JEDEC JESD51-6 with the board horizontal.
The board designer can choose between several types of heat sinks to place on the
PC755. There are several commercially-available heat sinks for the PC755 provided by
the following vendors:
For the exposed-die packaging technology, shown in Table 5, the intrinsic conduction
thermal resistance paths are as follows:
The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
The die junction-to-ball thermal resistance
Figure 6 depicts the primary heat transfer path for a package with an attached heat sink
mounted to a printed-circuit board.
Heat generated on the active side of the chip is conducted through the silicon, then
through the heat sink attach material (or thermal interface material), and finally to the
heat sink where it is removed by forced-air convection.
Since the silicon thermal resistance is quite small, for a first-order analysis, the tempera-
ture drop in the silicon may be neglected. Thus, the heat sink attach material and the
heat sink conduction/convective thermal resistances are the dominant terms.
Table 7.
Package Thermal Characteristics for HiTCE Package
Characteristic
Symbol
Value
Unit
°
C/W
°
C/W
PC755 HiTCE
Junction-to-bottom of balls
(1)
R
θ
J
R
θ
JMA
6.8
Junction-to-ambient thermal resistance, natural
convection, four-layer (2s2p) board
(1)(2)
20.7
Junction to board thermal resistance
R
θ
JB
11.0
°
C/W
Table 8.
Package Thermal Characteristics for CI-CGA
Characteristic
Symbol
Value
Unit
°
C/W
PC755 CI-CGA
Junction to board thermal resistance
R
θ
JB
8.42
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