參數(shù)資料
型號(hào)： PC755
廠商： Atmel Corp.
英文描述： PowerPC 755/745 RISC Microprocessor
中文描述： RISC微處理器PowerPC的745分之755
文件頁數(shù)： 32/50頁
文件大?。?/td> 1064K
代理商： PC755
32
PC755/745
2138D–HIREL–06/03
IEEE 1149.1 AC Timing
Specifications
Timing Specifications
Table 17 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure
18, Figure 19, Figure 20, and Figure 21.
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-
tion. The output timings are measured at the pins. All output timings assume a purely resistive 50
load (See Figure 18).
Time
-
of
-
flight delays must be added for trace lengths, vias, and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non
-
JTAG signal input timing with respect to TCK.
4. Non
-
JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC755.
Figure 18.
ALTERNATE AC Test Load for the JTAG Interface
Table 17.
JTAG AC Timing Specifications (Independent of SYSCLK)
(1)
Parameter
Symbol
Min
Max
Unit
TCK Frequency of operation
f
TCLK
0
16
MHz
TCK Cycle time
f
TCLK
62.5
-
ns
TCK Clock pulse width measured at 1.4V
t
JHJL
31
-
ns
TCK Rise and fall times
t
JR
& t
JF
0
2
ns
TRST Assert time
(2)
tTRST
25
-
ns
Input Setup Times:
(3)
Boundary
-
scan data
TMS, TDI
t
DVJH
t
IVJH
4
0
-
-
ns
Input Hold Times:
(3)
Boundary
-
scan data
TMS, TDI
t
DXJH
t
IXJH
15
12
-
-
ns
Valid Times:
(4)
Boundary
-
scan data
TDO
t
JLDV
t
JLOV
-
-
4
4
ns
Output Hold Times:
(4)
Boundary
-
scan data
TDO
t
JLDV
t
JLOV
25
12
-
-
ns
TCK to output high impedance:
(4)(5)
Boundary
-
scan data
TDO
t
JLDZ
t
JLOZ
3
3
19
9
ns
OVDD/2
OUTPUT
Z0 = 50
R
L
= 50
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