參數(shù)資料
型號: PCA9698DGG,512
廠商: NXP Semiconductors
文件頁數(shù): 10/48頁
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 35
接口: I²C
輸入/輸出數(shù): 40
中斷輸出:
頻率 - 時鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
包括: POR
產(chǎn)品目錄頁面: 826 (CN2011-ZH PDF)
其它名稱: 568-3241-5
935278614512
PCA9698DGG
18
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
Figure 7-2.
Data Memory Map
7.3.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU cycles as described in Figure 7-3.
Figure 7-3.
On-chip Data SRAM Access Cycles
7.4
EEPROM Data Memory
The ATmega328P contains 1K byte of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
“Memory Programming” on page 286 contains a detailed description on EEPROM Programming
in SPI or Parallel Programming mode.
32 Registers
64 I/O Registers
Internal SRAM
(2048 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x08FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
0x0100
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
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