參數(shù)資料
型號： PCA9698DGG,512
廠商： NXP Semiconductors
文件頁數(shù)： 36/48頁
文件大?。?/td> 0K
描述： IC I/O EXPANDER I2C 40B 56TSSOP
產(chǎn)品培訓模塊： I²C Bus Fundamentals
特色產(chǎn)品： NXP - I2C Interface
標準包裝： 35
接口： I²C
輸入/輸出數(shù)： 40
中斷輸出： 是
頻率 - 時鐘： 1MHz
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 56-TSSOP
包裝： 管件
包括： POR
產(chǎn)品目錄頁面： 826 (CN2011-ZH PDF)
其它名稱： 568-3241-5
935278614512
PCA9698DGG
41
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
9.10.4
Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-
age Reference” on page 48 for details on the start-up time.
9.10.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consump-
tion. Refer to “Watchdog Timer” on page 49 for details on how to configure the Watchdog Timer.
9.10.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
I/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 70 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to V
CC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
9.10.7
On-chip Debug System
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the
main clock source is enabled and hence always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
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PCA9698DGGT 制造商:NXP Semiconductors 功能描述:I2C GPIO Expander 5.5V 56-Pin TSSOP T/R
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