參數(shù)資料
型號(hào): PCA9698DGG,512
廠商: NXP Semiconductors
文件頁(yè)數(shù): 48/48頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 35
接口: I²C
輸入/輸出數(shù): 40
中斷輸出:
頻率 - 時(shí)鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
包括: POR
產(chǎn)品目錄頁(yè)面: 826 (CN2011-ZH PDF)
其它名稱: 568-3241-5
935278614512
PCA9698DGG
PCA9698
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 3 August 2010
9 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
7.3.1 5-bank register category
IP – Input registers
OP – Output registers
PI – Polarity Inversion registers
IOC – I/O Configuration registers
MSK – Mask interrupt registers
If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically
incremented after a read or write. This allows the user to program and/or read the
5 register banks sequentially.
If more than 5 bytes of data are written and AI = 1, previous data in the selected registers
will be overwritten or reread. Reserved registers are skipped and not accessed (refer to
If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not
incremented after data is read or written, only one register will be repeatedly read or
written.
7.3.2 1-bank register category
OUTCONF – Output Structure Configuration register
ALLBNK – All Bank Control register
MODE – Mode Selection register
If more than 1 byte of data is written or read, previous data in the same register is
overwritten independently of the value of AI.
7.4 Register definitions
Table 3.
Register summary
Reg #
D5
D4
D3
D2
D1
D0
Name
Type
Function
Input Port registers
00h
0
IP0
read only
Input Port register bank 0
01h
0
1
IP1
read only
Input Port register bank 1
02h
0
1
0
IP2
read only
Input Port register bank 2
03h
0
1
IP3
read only
Input Port register bank 3
04h
0
1
0
IP4
read only
Input Port register bank 4
05h
0
1
0
1
-
reserved for future use
06h
0
1
0
-
reserved for future use
07h
0
1
-
reserved for future use
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