參數(shù)資料
型號: PCA9698DGG,512
廠商: NXP Semiconductors
文件頁數(shù): 13/48頁
文件大小: 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
產(chǎn)品培訓(xùn)模塊: I²C Bus Fundamentals
特色產(chǎn)品: NXP - I2C Interface
標(biāo)準(zhǔn)包裝: 35
接口: I²C
輸入/輸出數(shù): 40
中斷輸出:
頻率 - 時鐘: 1MHz
電源電壓: 2.3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
包括: POR
產(chǎn)品目錄頁面: 826 (CN2011-ZH PDF)
其它名稱: 568-3241-5
935278614512
PCA9698DGG
20
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
7.5.1
General Purpose I/O Registers
The ATmega328P contains three General Purpose I/O Registers. These registers can be used
for storing any information, and they are particularly useful for storing global variables and Sta-
tus Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.6
Register Description
7.6.1
EEARH and EEARL – The EEPROM Address Register
Bits 15..9 – Res: Reserved Bits
These bits are reserved bits in the ATmega328P and will always read as zero.
Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
256/512/512/1K bytes EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 255/511/511/1023. The initial value of EEAR is undefined. A proper value must
be written before the EEPROM may be accessed.
EEAR8 is an unused bit in ATmega328P and must always be written to zero.
7.6.2
EEDR – The EEPROM Data Register
Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit
151413
12
1110
9
8
––
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
76
54
32
10
Read/Write
RR
R
R/W
Initial Value
0
X
XX
Bit
7
65
43
21
0
MSB
LSB
EEDR
Read/Write
R/W
Initial Value
0
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