- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4029 > PCX7447AVGH1000NB (Atmel)IC MPU 32BIT 1000MHZ 360CBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | PCX7447AVGH1000NB |
| 廠商： | Atmel |
| 文件頁數(shù)： | 16/52頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 1000MHZ 360CBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 處理器類型： | PowerPC 32-位 RISC |
| 速度： | 1.0GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 360-CBGA（25x25） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
23
0833E–HIREL–01/07
e2v semiconductors SAS 2007
PC7447A
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals; VDD supplies power to the processor core and the
PLL (after filtering to become AVDD). To program the I/O voltage, connect BVSEL to either GND (selects 1.8V), or to
HRESET or OV
DD (selects 2.5V); see Table 6-3 on page 11. If used, the pull-down resistor should be less than 250.
Because these settings may change in future products, it is recommended BVSEL be configured using resistor options,
jumpers, or some other flexible means, with the capability to reconfigure the termination of this signal in the future if neces-
sary. For actual recommended value of V
IN or supply voltages see Table 6-2 on page 10.
2. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OVDD.
3. These pins require weak pull-up resistors (for example, 4.7 K
) to maintain the control signals in the negated state after they
have been actively negated and released by the PC7447A and other bus masters.
4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
5. This signal must be negated during reset, by pull-up resistor to OV
DD or negation by HRESET (inverse of HRESET), to
ensure proper operation.
6. Internal pull up on die.
7. Ignored in 60x bus mode.
8. These signals must be pulled down to GND if unused, or if the PC7447A is in 60x bus mode.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
11. These signals are for factory use only and must be left unconnected for normal machine operation. Some pins that were
NCs on the PC7447, have now been defined for other purposes.
12. These input signals are for factory use only and must be pulled up to OV
DD for normal machine operation.
13. This pin can externally cause a performance monitor event. Counting of the event is enabled through software.
14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
15. These pins were NCs on the PC7447. They may be left unconnected for backward compatibility with these devices, but it is
recommended they be connected in new designs to facilitate future products. See section “Connection Recommendations”
on page 41 for more information.
16. These pins were OVDD pins on the PC7447. These pins are internally connected to OVDD and are intended to allow an exter-
nal device to detect the I/O voltage level present inside the device package. If unused, they must be connected directly to
OV
DD or left unconnected.
17. These pins provide connectivity to the on-chip temperature diode that can be used to determine the die junction temperature
of the processor. These pins may be left unterminated if unused.
TEST[0:3](12)
A12, B6, B10, E10
–
Input
BVSEL
D10
–
Input
BVSEL
F1
High
Input
BVSEL
A5
Low
Input
BVSEL
L4
Low
I/O
BVSEL
TSIZ[0:2]
G6, F7, E7
High
Output
BVSEL
TT[0:4]
E5, E6, F6, E9, C5
High
I/O
BVSEL
WT(3)
D3
Low
Output
BVSEL
VDD
H8, H10, H12, J7, J9, J11, J13, K8, K10, K12, K14, L7, L9, L11, L13,
M8, M10, M12
––
N/A
V
DD
A13, A16, A18, B17, B19, C13, E13, E16, F12, F17, F19, G11, G16,
H14, H17, H19, M14, M16, M18, N15, N17, P16, P18
––
N/A
V
DD_SENSE
G13, N12
–
N/A
Table 8-1.
Pinout Listing for the PC7447A, 360 HITCE Package (Continued)
Signal Name
Pin Number
Active
I/O
I/F Select(1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V07L55J8 | IC SRAM 256KBIT 55NS 68PLCC |
| IDT7007L55J8 | IC SRAM 256KBIT 55NS 68PLCC |
| ASC19DTEN | CONN EDGECARD 38POS .100 EYELET |
| ASC19DTEH | CONN EDGECARD 38POS .100 EYELET |
| AMC18DTEN | CONN EDGECARD 36POS .100 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCX7447AVGH1167NB | 功能描述:IC MPU 32BIT 1167MHZ 360CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| PCX7448MGH1000NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
| PCX7448MGH1250NC | 制造商:e2v technologies 功能描述:PCX7448MGH1250NC - Trays |
| PCX7448VGH1000NC | 制造商:e2v technologies 功能描述:PCX7448VGH1000NC - Trays |
| PCX7448VGH1250NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。