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參數(shù)資料
型號(hào)： PCX7447AVGH1000NB
廠商： Atmel
文件頁(yè)數(shù)： 36/52頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT 1000MHZ 360CBGA
標(biāo)準(zhǔn)包裝： 44
處理器類型： PowerPC 32-位 RISC
速度： 1.0GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 360-CBBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 360-CBGA（25x25）
包裝： 托盤(pán)
41
0833E–HIREL–01/07
e2v semiconductors SAS 2007
PC7447A
12.2
PLL Power Supply Filtering
The AV
DD power signal is provided on the PC7447A to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AV
DD input signal should be filtered of any
noise in the 500 KHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown
in Figure 12-1 using surface mount capacitors with minimum effective series inductance (ESL) is
recommended.
The circuit should be placed as close as possible to the AV
DD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AV
DD pin, which is on the periphery
of the 360 HITCE footprint.
Figure 12-1. PLL Power Supply Filter Circuit
12.3
Decoupling Recommendations
Due to the PC7447A dynamic power management feature, large address and data buses, and high
operating frequencies, the PC7447A can generate transient power surges and high frequency noise in
its power supply, especially while driving large capacitive loads. This noise must be prevented from
reaching other components in the PC7447A system, and the PC7447A itself requires a clean, tightly reg-
ulated source of power. Therefore, it is recommended that the system designer use sufficient decoupling
capacitors, typically one capacitor for every 1-2 V
DD pins, and a similar or lesser amount for the OVDD
pins, placed as close as possible to the power pins of the PC7447A. It is also recommended that these
decoupling capacitors receive their power from separate V
DD, OVDD, and GND power planes in the PCB,
utilizing short traces to minimize inductance.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic surface mount technology (SMT)
capacitors should be used to minimize lead inductance. Orientations where connections are made along
the length of the part, such as 0204, are preferable but not mandatory. Consistent with the recommenda-
tions of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall,
1993) and contrary to previous recommendations for decoupling Freescale
microprocessors, multiple
small capacitors of equal value are recommended over using multiple values of capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
DD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response
time necessary. They should also be connected to the power and ground planes through two vias to min-
imize inductance. Suggested bulk capacitors are: 100-330 F (AVX TPS tantalum or Sanyo OSCON).
12.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unless otherwise noted, unused active low inputs should be tied to OV
DD, and unused active high
inputs should be connected to GND. All NC (no connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD, OVDD, and GND pins in the PC7447A.
VDD
10
2.2
F
2.2
F
GND
AVDD
Low ESL surface mount capacitors
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參數(shù)描述
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PCX7448MGH1000NC 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays
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PCX7448VGH1250NC 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays
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