2. The symbology used for timing specifications herein follows the pattern o" />
參數(shù)資料
型號(hào)： PCX7447AVGH1000NB
廠商： Atmel
文件頁(yè)數(shù)： 21/52頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT 1000MHZ 360CBGA
標(biāo)準(zhǔn)包裝： 44
處理器類型： PowerPC 32-位 RISC
速度： 1.0GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 360-CBBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 360-CBGA（25x25）
包裝： 托盤
28
0833E–HIREL–01/07
PC7447A
e2v semiconductors SAS 2007
2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and
t
(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to
the SYSCLK reference (K) going to the high (H) state or input setup time. And t
KHOV symbolizes the time from SYSCLK (K)
going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal
(I) went invalid (X) with respect to the rising clock edge (KH) (note the position of the reference and its state for inputs) and
output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
3. tSYSCLK is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low and precharged high
before returning to high impedance, as shown in Figure 9-3 on page 29. The nominal precharge width for TS is 0.5 × tSYSCLK,
that is, less than the minimum t
SYSCLK period, to ensure that another master asserting TS on the following clock will not con-
tend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for
precharge.The high-impedance behavior is guaranteed by design.
5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following
AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any master asserting it low
in the first clock following AACK will then go to high impedance for 1 clock before precharging it high during the second cycle
after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK; that is, it should be high impedance as
shown in Figure 9-3 on page 29 before the first opportunity for another master to assert ARTRY. Output valid and output hold
timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.
7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Tim-
ing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for up to an entire
cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width for SHD0 and SHD1 is
1.0 tSYSCLK. The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).
8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters
represent the input setup and hold times for each sample. These values are guaranteed by design and not tested. These
inputs must remain stable after the second sample. See Figure 9-2 on page 28 for sample timing.
Figure 9-2 provides the mode select input timing diagram for the PC7447A. The mode select inputs are
sampled twice, once before and once after HRESET negation.
Figure 9-2.
Mode Input Sample Timing Diagram
HRESET
Mode Signals
VM
VM = Midpoint Voltage (OVDD/2)
SYSCLK
1st Sample
2nd Sample
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