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參數(shù)資料
| 型號(hào)： | PCX7447AVGH1000NB |
| 廠商： | Atmel |
| 文件頁數(shù)： | 39/52頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 1000MHZ 360CBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 處理器類型： | PowerPC 32-位 RISC |
| 速度： | 1.0GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 360-CBGA（25x25） |
| 包裝： | 托盤 |
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44
0833E–HIREL–01/07
PC7447A
e2v semiconductors SAS 2007
12.7
JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture.
While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals,
more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-
on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP)
function, simply tying TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The
COP interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage moni-
tors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must
be merged into these signals with logic.
The arrangement shown in Figure 12-3 on page 45 allows the COP port to independently assert
HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and
COP header will not be used, TRST should be tied to HRESET through a 0
. isolation resistor so that it
is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is
initialized during power-on. Although Freescale recommends that the COP header be designed into the
system as shown in Figure 12-3 on page 45, if this is not possible, the isolation resistor will allow future
access to TRST in the case where a JTAG interface may need to be wired onto the system in debug
situations.
The COP header shown in Figure 12-3 on page 45 adds many benefits: breakpoints, watchpoints, regis-
ter and memory examination/modification, and other standard debugger features are possible through
this interface, and can be as inexpensive as an unpopulated footprint for a header to be added when
needed.
The COP interface has a standard header for connection to the target system, based on the 0.025 inch
square-post, 0.100 inch centered header assembly (often called a Berg header). The connector typically
has pin 14 removed as a connector key.
There is no standardized way to number the COP header shown in Figure 12-3 on page 45; conse-
quently, many different pin numbers have been observed from emulator vendors. Some are numbered
top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number
the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement
recommended in Figure 12-3 on page 45 is common to all known emulators.
The QACK signal shown in Figure 12-3 on page 45 is usually connected to the PCI bridge chip in a sys-
tem and is an input to the PC7447A informing it that it can go into the quiescent state. Under normal
operation this occurs during a low-power mode selection. In order for COP to work, the PC7447A must
see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive
this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Addition-
ally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for
these tools, a pull-up resistor can be implemented to ensure this signal is negated when it is not being
driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclu-
sive and it is never necessary to populate both in a system. To preserve correct power-down operation,
QACK should be merged through logic so that it also can be driven by the PCI bridge.
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| PCX7447AVGH1167NB | 功能描述:IC MPU 32BIT 1167MHZ 360CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| PCX7448MGH1000NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
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| PCX7448VGH1000NC | 制造商:e2v technologies 功能描述:PCX7448VGH1000NC - Trays |
| PCX7448VGH1250NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
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