參數(shù)資料
型號： PCX7447AVGH1000NB
廠商： Atmel
文件頁數(shù)： 18/52頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 1000MHZ 360CBGA
標(biāo)準(zhǔn)包裝： 44
處理器類型： PowerPC 32-位 RISC
速度： 1.0GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 360-CBBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 360-CBGA（25x25）
包裝： 托盤
25
0833E–HIREL–01/07
e2v semiconductors SAS 2007
PC7447A
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
4. The leakage is measured for nominal OV
DD/GVDD and VDD, or both OVDD/GVDD and VDD must vary in the same direction (for
example, both OV
DD and VDD vary by either +5% or -5%).
5. Capacitance is periodically sampled rather than 100% tested.
6. Excludes signals with internal pull ups: BVSEL, LSSD_MODE, TDI, TMS, and TRST. Characterization of leakage current for
these signals is currently being conducted.
9.2
Dynamic Characteristics
This section provides the AC electrical characteristics for the PC7447A. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section “Clock AC Specifications” on
page 25 and tested for conformance to the AC specifications for that frequency. The processor core fre-
quency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals,
and can be dynamically modified using dynamic frequency switching (DFS). Parts are sold by maximum
processor core frequency; See “Ordering Information” on page 46. for information on ordering parts.
9.2.1
Clock AC Specifications
Table 9-2 provides the clock AC timing specifications as defined in Figure 9-1 on page 26 and repre-
sents the tested operating frequencies of the devices. The maximum system bus frequency, f
SYSCLK,
given in Table 9-2 on page 25 is considered a practical maximum in a typical single-processor system.
The actual maximum SYSCLK frequency for any application of the PC7447A will be a function of the AC
timings of the PC7447A, the AC timings for the system controller, bus loading, printed-circuit board
topology, trace lengths, and so forth, and may be less than the value given in Table 9-2 on page 25.
Table 9-2.
Clock AC Timing Specifications (See Table 6-2 on page 10 for Recommended Operating Conditions)
Symbol
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000 MHz
1267 MHz
1333 MHz
1420 MHz
VDD = 1.3V
VDD = 1.3
MinMax
Min
Max
MinMax
f
CORE
Processor core
frequency
600
1000
600
1267
600
1333
600
1420
MHz
f
VCO
VCO frequency
1200
2000
1200
2533
1200
2667
1200
2840
MHz
f
SYSCLK
SYSCLK frequency
33
167
33
167
33
167
33
167
MHz
tSYSCLK
SYSCLK cycle time
6.0
30
6
30
6
30
6
30
ns
tKR, tKF
SYSCLK rise and fall
time
–
1.0
–
1–1–1
ns
t
KHKL/tSYSCLK
SYSCLK duty cycle
measured at OV
DD/2
40
60
40
60
40
60
40
60
%
–
150
–
150
–
150
–
150
ps
Internal PLL relock
–
100
–
100
–
100
–
100
s
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