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參數(shù)資料
| 型號： | PCX7447AVGH1000NB |
| 廠商： | Atmel |
| 文件頁數(shù)： | 23/52頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 1000MHZ 360CBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 處理器類型： | PowerPC 32-位 RISC |
| 速度： | 1.0GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-CBBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 360-CBGA（25x25） |
| 包裝： | 托盤 |
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3
0833E–HIREL–01/07
e2v semiconductors SAS 2007
PC7447A
2.
Features
This section summarizes features of the PC7447A implementation of the PowerPC architecture.
Major features of the PC7447A are as follows:
High-performance, superscalar microprocessor
– Up to four instructions can be fetched from the instruction cache at a time
– Up to 12 instructions can be in the instruction queue (IQ)
– Up to 16 instructions can be at some stage of execution simultaneously
– Single-cycle execution for most instructions
– One instruction per clock cycle throughput for most instructions
– Seven-stage pipeline control
Eleven independent execution units and three register files
– Branch processing unit (BPU) features static and dynamic branch prediction
128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache
of branch instructions that have been encountered in branch/loop code sequences. If a
target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it
can be made available from the instruction cache. Typically, a fetch that hits the BTIC
provides the first four instructions in the target stream.
2048-entry branch history table (BHT) with two bits per entry for four levels of prediction: not
taken, strongly not taken, taken, and strongly taken
Up to three outstanding speculative branches
Branch instructions that do not update the count register (CTR) or link register (LR) are often
removed from the instruction stream
Eight-entry link register stack to predict the target address of Branch Conditional to Link
Register (BCLR) instructions
– Four integer units (IUs) that share 32 GPRs for integer operands
Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except
multiply, divide, and move to/from special-purpose register instructions.
IU2 executes miscellaneous instructions including the CR logical operations, integer
multiplication and division instructions, and move to/from special-purpose register
instructions.
– Five-stage FPU and a 32-entry FPR file
Fully IEEE
754-1985-compliant FPU for both single- and double-precision operations
Supports non-IEEE mode for time-critical operations
Hardware support for denormalized number
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCX7447AVGH1167NB | 功能描述:IC MPU 32BIT 1167MHZ 360CBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:SCC 處理器類型:Z380 特點(diǎn):全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
| PCX7448MGH1000NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
| PCX7448MGH1250NC | 制造商:e2v technologies 功能描述:PCX7448MGH1250NC - Trays |
| PCX7448VGH1000NC | 制造商:e2v technologies 功能描述:PCX7448VGH1000NC - Trays |
| PCX7448VGH1250NC | 制造商:e2v technologies 功能描述:MPU RISC 32BIT 0.09UM 1.25GHZ 1.5V/1.8V/2.5V 360HITCE CBGA - Trays |
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