參數(shù)資料
型號: PCX7447AVGH1000NB
廠商: Atmel
文件頁數(shù): 24/52頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 1000MHZ 360CBGA
標(biāo)準(zhǔn)包裝: 44
處理器類型: PowerPC 32-位 RISC
速度: 1.0GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 360-CBBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 360-CBGA(25x25)
包裝: 托盤
30
0833E–HIREL–01/07
PC7447A
e2v semiconductors SAS 2007
9.2.3
IEEE 1149.1 AC Timing Specifications
Table 9-4 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 9-5 through
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-
tion. The output timings are measured at the pins. All output timings assume a purely resistive 50
load (see Figure 9-4).
Time-of-flight delays must be added for trace lengths, vias and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The time is for test purposes only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization.
Figure 9-4 provides the AC test load for TDO and the boundary-scan outputs of the PC7457.
Figure 9-4.
Alternate AC Test Load for the JTAG Interface
Table 9-4.
JTAG AC Timing Specifications (Independent of SYSCLK)(1)at Recommended Operating Conditions
Symbol
Parameter
Min
Max
Unit
fTCLK
TCK frequency of operation
0
33.3
MHz
tTCLK
TCK cycle time
30
ns
t
JHJL
TCK clock pulse width measured at 1.4V
15
ns
tJR and tJF
TCK rise and fall times
2
ns
tTRST
TRST assert time
25
ns
tDVJH
tIVJH
Input Setup Times:
Boundary-scan data
TMS, TDI
4
0
ns
tDXJH
t
IXJH
Input Hold Times:
Boundary-scan data
TMS, TDI
20
25
ns
t
JLDV
tJLOV
Valid Times:
Boundary-scan data
TDO
4
20
25
ns
t
JLDX
tJLOX
Output hold times:
Boundary-scan data
TDO
30
tJLDZ
t
JLOZ
TCK to output high impedance:
Boundary-scan data
TDO
3
19
9
ns
Output
Z0 = 50
RL = 50
OVDD/2
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