參數(shù)資料
型號(hào)： PDI1394L11
廠商： NXP Semiconductors N.V.
英文描述： 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器)
中文描述： 1394影音鏈路層控制器（視聽（音頻/視頻）鏈接層控制器）
文件頁數(shù)： 22/46頁
文件大?。?/td> 294K
代理商： PDI1394L11
Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
22
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
PHY packet first quadlet
1110
2
0000
2
SV00265
31 30
Figure 20. PHY Packet Receive Format
For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified
and is not included.
12.5.2.5
After a packet from one of the queues has been transmitted, the asynchronous transmitter assembles a confirmation (see Figure 21) which is
used to confirm the result of the transmission to the higher layers. Separate confirmations are assembled for request and response
transmissions. Request confirmations are written into the request queue and response confirmations are written into the response queue.
Transaction data confirmation formats
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
conf
destinationID
tLabel
3130
1000
2
00
2
SV00821
Figure 21. Request and response confirmation format
Table 7. Confirmation codes
CODE
1
0
DESCRIPTION
Non-broadcast packet transmitted; addressed node returned no acknowledge.
1
Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete.
2
Non-broadcast packet transmited; addressed node returned an acknowledge pending.
4
Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries.
D
16
E
16
Acknowledge data error received (transaction complete).
Acknowledge type error received (transaction complete).
NOTE:
1. All other codes are reserved.
For every packet written in a transmitter queue by the CPU, there will be one confirmation written in the corresponding receiver queue by the AV
layer logic.
12.5.3
The PDI1394L11 provides a single interrupt line (HIF INT_N) for connection to a host controller. Status indications from four major areas of the
device are collected and ORed together to activate HIF INT_N. Status from four major areas of the device are collected in four status registers;
LNKPHYINTACK, ITXINTACK, IRXINTACK, and ASYINTACK. At this level, each individual status can be enabled to generate a chip-level
interrupt by activating HIF INT_N. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt
is indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be
acknowledged. To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, or ASYINTACK causing
the interrupt status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect.
Interrupts
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394L11BA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 AV link layer controller
PDI1394L11BA-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller
PDI1394L21 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
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