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參數(shù)資料
| 型號： | PDI1394L11 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器) |
| 中文描述： | 1394影音鏈路層控制器（視聽（音頻/視頻）鏈接層控制器） |
| 文件頁數(shù)： | 28/46頁 |
| 文件大?。?/td> | 294K |
| 代理商： | PDI1394L11 |
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Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
28
13.1
Link Control Registers
13.1.1
ID Register (IDREG) – Base Address: 0x000
The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00272
NODE ID
BUS ID
VERSION_CODE
3130
Reset Value 0xFFFF0002
Bit 31..22:
R/W
Bus ID:The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to
accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.
Node ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject
incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.
Version_Code: Version of the PDI1394L11
Bit 21..16:
R/W
Bit 15..0:
R
13.1.2
The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also
provides general link status.
General Link Control (LNKCTL) – Base Address: 0x004
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
6
5 4 3
2 1
0
SV00273
I
R
R
B
C
S
C
C
R
R
T
R
BSYCTRL
ATACK
31 30
Reset Value 0x46000000
Bit 31:
R/W
ID Valid: When equal to one, the PDI1394L11 accepts the packets addressed to this node. This bit is automatically
set after selfID complete and node ID is updated.
Receive Self ID: When asserted, the self-identification packets, generated by each PHY device on the bus, during
bus initialization are received and placed into the asynchronous request queue as a single packet.
Busy Control: These bits control what busy status the chip returns to incoming packets. The field is defined below:
000 = use protocol requested by received packet (either dual phase or single phase)
001 = send busy A when it is necessary to send a busy acknowledge (testing/diagnostics)
010 = send a busy B when it is necessary to send a busy acknowledge (testing/diagnostics)
011 = use single phase retry protocol
100 = use protocol requested in packet, always send a busy ack (for all packets)
101 = busy A all incoming packets
110 = busy B all incoming packets are ‘1’
111 = use single phase retry protocol, always send a busy ack
Transmitter Enable: When this bit is set, the link layer transmitter will arbitrate and send packets.
Receiver Enable: When this bit is set, the link layer receiver will receive and respond to bus packets.
Reset Transmitter: When set to one, this synchronously resets the transmitter within the link layer.
Reset Receiver: When set to one, this synchronously resets the receiver within the link layer.
Strict Isochronous: Used to accept or reject isochronous packets sent outside of specified isochronous cycles
(between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified cycles, a “0” accepts
isochronous packets sent outside the specified cycle.
Cycle Master: When asserted and the PDI1394L11 is attached to the root PHY (ROOT bit = 1), and the cycle_count
field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master function will be
disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle Master function in
such a case, first reset CYMASTER, then set it again.
Bit 30:
R/W
Bit 29..27:
R/W
Bit 26:
Bit 25:
Bit 21:
Bit 20:
Bit 12:
R/W
R/W
R/W
R/W
R/W
Bit 11:
R/W
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| PDI1394P21 | 3-port Physical Layer Interface(三端口物理層接口) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L11BA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 AV link layer controller |
| PDI1394L11BA-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller |
| PDI1394L21 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
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