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參數(shù)資料
| 型號： | PDI1394L11 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器) |
| 中文描述： | 1394影音鏈路層控制器（視聽（音頻/視頻）鏈接層控制器） |
| 文件頁數(shù)： | 29/46頁 |
| 文件大?。?/td> | 294K |
| 代理商： | PDI1394L11 |
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Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
29
Bit 10:
R/W
Cycle Source: When asserted, the cycle_count field increments and the cycle_offset field resets for each positive
transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field rolls over.
Cycle Timer Enable: When asserted, the cycle offset field increments.
Root: Indicates this device is the root on the bus. This automatically updates after the self_ID phase.
Busy Flag: The type of busy acknowledge which will be sent next time an acknowledge is required. 0 = Busy A,
1 = Busy B (only meaningful during a dual-phase busy/retry operation).
AT acknowledge received: The last acknowledge received by the transmitter in response to a packet sent from the
transmit-FIFO interface while the ATF is selected (diagnostic purposes).
Bit 9:
Bit 5:
Bit 4:
R/W
R
R
Bit 3..0:
R
13.1.3
The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to
generate an interrupt. The interrupt enable register (LNKPHYINTE) is a mirror of this register. Acknowledgment of an interrupt is accomplished
by writing a ‘1’ to a bit in this register that is set. This action reset the bit indication to a ‘0’. Writing a ‘1’ to a bit that is already “0” will have no
effect on the register.
Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00274
C
F
H
T
A
P
S
R
I
A
P
T
C
P
C
C
C
C
C
3130
Reset Value 0x00000000
Bit 18:
Bit 17:
Bit 16:
Bit 15:
Bit 14:
Bit 13:
R/W
R/W
R/W
R/W
R/W
R/W
Command Reset Received: A write request to RESET-START has been received.
Fair Gap: The serial bus has been idle for a fair-gap time (called subaction gap in the IEEE 1394 specification).
Arbitration Reset Gap: The serial bus has been idle for an arbitration reset gap.
Phy Chip Int: The Phy chip has signaled an interrupt through the Phy interface.
Phy Register Information Received: A register has been transferred by the Physical Layer device into the Link.
Phy Reset Started: A Phy-layer reconfiguration has started. This interrupt clears the ID valid bit. (Called Bus Reset
in the IEEE 1394 specification).
Transmitter Ready: The transmitter is idle and ready.
Receiver has Data: The receiver has confirmed data to the receiver response/request FIFO. Used for diagnostic
purposes only.
Isochronous Transmitter is Stuck: The transmitter has detected invalid data at the transmit-FIFO interface when the
ITF is selected.
Asynchronous Transmitter is Stuck: The transmitter expected start of new async packet in queue, but found other
data (out of sync with user). Reset to clear.
Busy Acknowledge Sent by Receiver: The receiver was forced to send a busy acknowledge to a packet addressed
to this node because the receiver response/request FIFO overflowed.
Header Error: The receiver detected a header CRC error on an incoming packet that may have been addressed to
this node.
Transaction Code Error: The transmitter detected an invalid transaction code in the data at the transmit FIFO
interface.
Cycle Timed Out. ISOCH cycle lasted more than 125
μ
s from Cycle-Start to Fair Gap: Disables cycle master function
Cycle Second incremented: The cycle second field in the cycle-timer register incremented. This occurs
approximately every second when the cycle timer is enabled.
Cycle Started: The transmitter has sent or the receiver has received a cycle start packet.
Cycle Done: A fair gap has been detected on the bus after the transmission or reception of a cycle start packet. This
indicates that the isochronous cycle is over; Note: Writing a value of ‘0’ to the bit has no effect.
Cycle Pending: Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and stays
asserted until the isochronous cycle has ended.
Cycle Lost: The cycle timer has rolled over twice without the reception of a cycle start packet. This only occurs when
cycle master is not asserted.
Bit 12:
Bit 11:
R/W
R/W
Bit 10:
R/W
Bit 9:
R/W
Bit 8:
R/W
Bit 7:
R/W
Bit 6:
R/W
Bit 5:
Bit 4:
R/W
R/W
Bit 3:
Bit 2:
R/W
R/W
Bit 1:
R/W
Bit 0:
R/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L11BA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 AV link layer controller |
| PDI1394L11BA-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller |
| PDI1394L21 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
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