
Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
39
13.3.7
Asynchronous Receive Request (RREQ) – Base Address: 0x098
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
RREQ
SV00297
3130
Reset Value 0x00000000
Bit 31..0:
R
Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading.
RREQ:Quadlet of packet from receiver request queue (transfer register).
13.3.8
Asynchronous Receive Response (RRSP) – Base Address: 0x09C
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
RRSP
SV00298
3130
Reset Value 0x00000000
Bit 31..0:
R
Reading this register will clear the RRSPQQAV flag until the next received quadlet is available for reading.
RRSP:Quadlet of packet from receiver response queue (transfer register).
13.3.9
Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0
SV00796
29 28
27 26 25 24 23
22 21 20 19 18
17 16
15 14 13
12 11 10
9
8
7
6
5
4
3
2
1
0
T
R
R
R
R
R
R
R
S
R
T
R
T
T
T
T
T
31 30
Reset Value 0x00000000
Bit 31..17:
Bit 16:
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Unused bits read ‘0’
RRSPQFULL: Receiver response queue did become full.
RREQQFULL: Receiver request queue did become full.
SIDQAV: Current quadlet in RREQ is selfID data.
RRSPQLASTQ: Current quadlet in RRSP is last quadlet of packet.
RREQQLASTQ: Current quadlet in RREQ is last quadlet of packet.
RRSPQRDERR: Receiver response queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access.
RREQQRDERR: Receiver request queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access.
RRSPQQAV: Receiver response queue quadlet available (in RRSP).
RREQQQAV: Receiver request queue quadlet available (in RREQ).
TIMEOUT: Split transaction response timeout.
RCVDRSP: Solicited response received (within timeout interval).
TRSPQFULL: Transmitter response queue did become full.
TREQQFULL: Transmitter request queue did become full.
TRSPQWRERR: Transmitter response queue write error (transfer error).
Bit 10:
R/W
Bit 9:
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
R/W
R/W
R/W
R/W
R/W
R/W
R/W