參數(shù)資料
型號(hào)： PDI1394L11
廠商： NXP Semiconductors N.V.
英文描述： 1394 AV Link Layer Controller(AV（音頻/視頻）鏈接層控制器)
中文描述： 1394影音鏈路層控制器（視聽（音頻/視頻）鏈接層控制器）
文件頁數(shù)： 34/46頁
文件大?。?/td> 294K
代理商： PDI1394L11
Philips Semiconductors
Product specification
PDI1394L11
1394 AV link layer controller
1997 Oct 21
34
13.2.7
The AV Transmitter Memory Status register reports on the condition of the internal memory buffer used to store incoming AV data streams
before transmission over the 1394 bus.
Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
I
I
I
I
SV00284
3130
Reset Value 0x00000003
Bit 3:
Bit 2:
Bit 1:
Bit 0:
R
R
R
R
ITXMF: memory is completely full, no storage available.
ITXMAF: almost full, exactly one quadlet of storage available.
ITXM5AV: at least 5 more quadlets of storage available.
ITXME: memory bank is empty (zero quadlets stored).
13.2.8
Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
E
R
E
S
R
C
T
R
F
S
I
I
SV00285
S
BPAD
3130
Reset Value 0x00000041
AV Receiver Control Bits.
R/W
RMVUAP: Remove unreliable packets from memory, do not attempt delivery
R
SPAV: Source packet available for delivery in buffer memory.
R/W
EN_IRX: Enable receiver operation. Value is only checked whenever a new bus packet arrives, so enable/disable
while running is ‘graceful’.
R/W
BPAD: Value indicating the amount of byte padding to be removed from the last data quadlet of each source
packet, from 0 to 3 bytes. This is in addition to quadlet padding as defined in IEC 61883 International Standard.
R/W
EN_FS: Enable processing of SYT stamps.
R/W
RST_IRX: causes the receiver to be reset when ‘1’. In order for synchronous reset of IRX to work properly, the
application must supply an AVCLK and ensure that the reset bit is kept (programmed) HIGH for at least the duration
of one AVCLK period. Failure to do so may cause the application interface of this module to be improperly reset (or
not reset at all).
Bit 6:
Bit 5:
Bit 4:
Bit 2..3:
Bit 1:
Bit 0:
13.2.9
This quadlet represents the last received header value when AV receiver is operating.
Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044
29 28 272625 24 23 22 212019 18 1716 15 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
S
QPC
FN
DBS
SV00286
E
F
3130
SID
Reset Value 0x00000000
Bit 31..30:
Bit 29..24
Bit 23.16:
Bit 15..14:
R
R
R
R
E0: End of Header, F0: Format: Always set to 00 for first AV header quadlet
SID: Source ID, contains the node address of the sender of the isochronous data.
DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets.
FN (Fraction Number): The encoding for the number of data blocks into which each source packet has been divided
(00 = 1, 01 = 2, 10 = 4, 11 = 8) by the transmitter of the packet.
QPC: Number of dummy quadlets appended to each source packet before it was divided into data blocks of the
specified size.
Bit 13..11:
R
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394L11BA 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 AV link layer controller
PDI1394L11BA-S 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IEEE 1394 (Firewire) Bus Interface/Controller
PDI1394L21 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
PDI1394L21BP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
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