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          參數(shù)資料
          型號(hào): PHD55N04LT
          英文描述: Triple 1.8V to 6V High-Side MOSFET Drivers; Package: PDIP; No of Pins: 8; Temperature Range: 0&deg;C to +70&deg;C
          中文描述: 晶體管| MOSFET的| N溝道| 35V的五(巴西)直| 55A條(?。﹟對(duì)252AA
          文件頁數(shù): 3/11頁
          文件大?。?/td> 117K
          代理商: PHD55N04LT
          Philips Semiconductors
          Product specification
          N-channel TrenchMOS
          transistor
          Logic level FET
          PHP55N04LT, PHB55N04LT
          PHD55N04LT
          REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
          T
          j
          = 25C unless otherwise specified
          SYMBOL PARAMETER
          I
          S
          Continuous source current
          (body diode)
          I
          SM
          Pulsed source current (body
          diode)
          V
          SD
          Diode forward voltage
          CONDITIONS
          MIN.
          -
          TYP. MAX. UNIT
          -
          55
          A
          -
          -
          220
          A
          I
          F
          = 25 A; V
          GS
          = 0 V
          I
          F
          = 55 A; V
          GS
          = 0 V
          I
          F
          = 20 A; -dI
          F
          /dt = 100 A/
          μ
          s;
          V
          GS
          = 0 V; V
          R
          = 25 V
          -
          -
          -
          -
          0.9
          1.0
          87
          0.1
          1.2
          -
          -
          -
          V
          t
          rr
          Q
          rr
          Reverse recovery time
          Reverse recovery charge
          ns
          μ
          C
          Fig.1. Normalised power dissipation.
          PD% = 100
          P
          D
          /P
          D 25 C
          = f(T
          mb
          )
          Fig.2. Normalised continuous drain current.
          ID% = 100
          I
          D
          /I
          D 25 C
          = f(T
          mb
          ); V
          GS
          5 V
          Fig.3. Safe operating area
          I
          D
          & I
          DM
          = f(V
          DS
          ); I
          DM
          single pulse; parameter t
          p
          Fig.4. Transient thermal impedance.
          Z
          th j-mb
          = f(t); parameter D = t
          p
          /T
          Normalised Power Derating, PD (%)
          0
          10
          20
          30
          40
          50
          60
          70
          80
          90
          100
          0
          25
          50
          75
          100
          125
          150
          175
          Mounting Base temperature, Tmb (C)
          1
          10
          100
          1000
          1
          10
          100
          Drain-Source Voltage, VDS (V)
          Peak Pulsed Drain Current, IDM (A)
          D.C.
          RDS(on) = VDS/ ID
          tp = 10 us
          100 us
          1 ms
          100 ms
          Normalised Current Derating, ID (%)
          0
          10
          20
          30
          40
          50
          60
          70
          80
          90
          100
          0
          25
          50
          75
          100
          125
          150
          175
          Mounting Base temperature, Tmb (C)
          0.01
          0.1
          1
          10
          1E-06
          1E-05
          1E-04
          1E-03
          1E-02
          1E-01
          1E+00
          Pulse width, tp (s)
          Transient thermal impedance, Zth j-mb (K/W)
          single pulse
          D = 0.5
          0.2
          0.1
          0.05
          0.02
          tp
          D = tp/T
          D
          P
          T
          January 2001
          3
          Rev 1.000
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