
PIC18FXXXX
DS21993C-page 166
2007 Microchip Technology Inc.
TRISE Register...................................................................37
IBF Bit .........................................................................38
IBOV Bit ......................................................................38
PSPMODE Bit.......................................................36, 37
TXSTA Register
SYNC Bit.....................................................................69
TRMT Bit.....................................................................69
TX9 Bit ........................................................................69
TX9D Bit......................................................................69
TXEN Bit .....................................................................69
U
UA.......................................................................................60
Universal Synchronous Asynchronous Receiver
Transmitter.
See
USART
Update Address bit, UA.......................................................60
USART................................................................................69
Asynchronous Mode ...................................................73
Asynchronous Receiver..............................................75
Asynchronous Reception............................................76
Associated Registers..........................................77
Asynchronous Transmission
Associated Registers..........................................75
Asynchronous Transmitter..........................................73
Baud Rate Generator (BRG).......................................71
Baud Rate Formula.............................................71
Baud Rates, Asynchronous Mode (BRGH = 0) ..72
Baud Rates, Asynchronous Mode (BRGH = 1) ..72
Sampling.............................................................71
Mode Select (SYNC Bit) .............................................69
Overrun Error (OERR Bit)...........................................70
RC6/TX/CK Pin.......................................................9, 11
RC7/RX/DT Pin.......................................................9, 11
Serial Port Enable (SPEN Bit).....................................69
Single Receive Enable (SREN Bit) .............................70
Synchronous Master Mode.........................................78
Synchronous Master Reception..................................80
Associated Registers..........................................81
Synchronous Master Transmission.............................78
Associated Registers..........................................79
Synchronous Slave Mode...........................................81
Synchronous Slave Reception....................................82
Associated Registers..........................................82
Synchronous Slave Transmission...............................81
Associated Registers..........................................82
Transmit Data, 9th Bit (TX9D).....................................69
Transmit Enable (TXEN Bit)........................................69
Transmit Enable, Nine-bit (TX9 Bit) ............................69
Transmit Shift Register Status (TRMT Bit)..................69
User Code.........................................................................103
W
Wake-up from SLEEP......................................................... 89
Interrupts .............................................................. 95, 96
MCLR Reset............................................................... 96
WDT Reset................................................................. 96
Wake-up from Sleep......................................................... 102
Wake-up Using Interrupts................................................. 102
Watchdog Timer (WDT).............................................. 89, 101
Associated Registers................................................ 101
Enable (WDTE Bit) ................................................... 101
Postscaler.
See
Postscaler, WDT
Programming Considerations................................... 101
RC Oscillator............................................................. 101
Time-out Period........................................................ 101
WDT Reset, Normal Operation....................... 93, 95, 96
WDT Reset, SLEEP........................................ 93, 95, 96
WCOL bit ............................................................................ 61
Write Collision Detect bit (WCOL) ...................................... 61
WWW Address ................................................................. 167
WWW, On-Line Support ....................................................... 4