參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 24/172頁
文件大小： 1506K
代理商： PIC16CR7X
PIC16CR7X
DS21993C-page 22
2007 Microchip Technology Inc.
2.2.2.4
PIE1 Register
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
PIE1: (ADDRESS 8Ch)
R/W-0
PSPIE
(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE
R/W-0
TMR2IE
R/W-0
TMR1IE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIE
(1)
:
Parallel Slave Port Read/Write Interrupt Enable bit
1
= Enables the PSP read/write interrupt
0
= Disables the PSP read/write interrupt
ADIE
: A/D Converter Interrupt Enable bit
1
= Enables the A/D converter interrupt
0
= Disables the A/D converter interrupt
RCIE
: USART Receive Interrupt Enable bit
1
= Enables the USART receive interrupt
0
= Disables the USART receive interrupt
TXIE
: USART Transmit Interrupt Enable bit
1
= Enables the USART transmit interrupt
0
= Disables the USART transmit interrupt
SSPIE
: Synchronous Serial Port Interrupt Enable bit
1
= Enables the SSP interrupt
0
= Disables the SSP interrupt
CCP1IE
: CCP1 Interrupt Enable bit
1
= Enables the CCP1 interrupt
0
= Disables the CCP1 interrupt
TMR2IE
: TMR2 to PR2 Match Interrupt Enable bit
1
= Enables the TMR2 to PR2 match interrupt
0
= Disables the TMR2 to PR2 match interrupt
TMR1IE
: TMR1 Overflow Interrupt Enable bit
1
= Enables the TMR1 overflow interrupt
0
= Disables the TMR1 overflow interrupt
PSPIE is reserved on 28-pin devices; always maintain this bit clear.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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