參數(shù)資料
型號(hào)： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 84/172頁
文件大?。?/td> 1506K
代理商： PIC16CR7X
PIC16CR7X
DS21993C-page 82
2007 Microchip Technology Inc.
TABLE 10-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
10.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don’t care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP
instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR reg-
ister will transfer the data to the RCREG register and if
enable bit RCIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
Follow these steps when setting up a Synchronous
Slave Reception:
1.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2.
If interrupts are desired, set enable bit RCIE.
3.
If 9-bit reception is desired, set bit RX9.
4.
To enable reception, set enable bit CREN.
5.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
6.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7.
Read the 8-bit received data by reading the
RCREG register.
8.
If any error occurred, clear the error by clearing
bit CREN.
9.
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
18h
19h
8Ch
98h
99h
Legend:
Note
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG
x
= unknown, – = unimplemented, read as ‘
0
’. Shaded cells are not used for synchronous slave transmission.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
PSPIF
(1)
SPEN
USART Transmit Data Register
PSPIE
(1)
ADIE
CSRC
TX9
Baud Rate Generator Register
ADIF
RX9
RCIF
SREN
TXIF
CREN
SSPIF
—
CCP1IF
FERR
TMR2IF TMR1IF
OERR
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
RX9D
RCIE
TXEN
TXIE
SYNC
SSPIE
—
CCP1IE TMR2IE TMR1IE
BRGH
TRMT
TX9D
1:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
x = unknown, – = unimplemented, read as ‘
0
’. Shaded cells are not used for synchronous slave reception.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices, always maintain these bits clear.
PSPIF
(1)
SPEN
USART Receive Data Register
PSPIE
(1)
ADIE
CSRC
TX9
Baud Rate Generator Register
ADIF
RX9
RCIF
SREN
TXIF
CREN
SSPIF
—
CCP1IF
FERR
TMR2IF
OERR
TMR1IF
RX9D
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
RCIE
TXEN
TXIE
SYNC
SSPIE
—
CCP1IE
BRGH
TMR2IE
TRMT
TMR1IE
TX9D
1:
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