參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 78/172頁
文件大小： 1506K
代理商： PIC16CR7X
PIC16CR7X
DS21993C-page 76
2007 Microchip Technology Inc.
FIGURE 10-4:
USART RECEIVE BLOCK DIAGRAM
FIGURE 10-5:
ASYNCHRONOUS RECEPTION
Steps to follow when setting up an Asynchronous
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (
Section 10.1 “USART Baud
Rate Generator (BRG)”
).
2.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3.
If interrupts are desired, then set enable bit
RCIE.
4.
If 9-bit reception is desired, then set bit RX9.
5.
Enable the reception by setting bit CREN.
6.
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
7.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
9.
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR Register
MSb
LSb
RX9D
RCREG Register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
Stop
Start
(8)
7
1
0
RX9
F
OSC
÷
64
or
÷
16
Start
bit
bit 7/8
bit 1
bit 0
bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX (pin)
Rcv Buffer Reg
Reg
Read Rcv
Buffer reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
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