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參數(shù)資料
| 型號(hào)： | PIC16CR7X |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 28/40-Pin, 8-Bit CMOS ROM Microcontrollers |
| 中文描述： | 28/40-Pin，8位微控制器的CMOS光盤 |
| 文件頁(yè)數(shù)： | 69/172頁(yè) |
| 文件大小： | 1506K |
| 代理商： | PIC16CR7X |
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2007 Microchip Technology Inc.
DS21993C-page 67
PIC16CR7X
FIGURE 9-6:
I
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
9.3.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then, pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time (Figure 9-7).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another occur-
rence of the Start bit. If the SDA line was low (ACK), the
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit CKP.
FIGURE 9-7:
I
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3
D4
D5
D6
D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK
Receiving Data
Receiving Data
D4
D5
D0
D1
D2
D3
D6
D7
ACK
R/W=
0
Receiving Address
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Transmitting Data
R/W =
1
Receiving Address
1
Data in
sampled
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
S
SCL held low
rewhile CPU
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