參數(shù)資料
型號： PIC16CR7X
廠商： Microchip Technology Inc.
英文描述： 28/40-Pin, 8-Bit CMOS ROM Microcontrollers
中文描述： 28/40-Pin，8位微控制器的CMOS光盤
文件頁數(shù)： 19/172頁
文件大?。?/td> 1506K
代理商： PIC16CR7X
2007 Microchip Technology Inc.
DS21993C-page 17
PIC16CR7X
Bank 1
80h
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
27, 96
81h
82h
(4)
83h
(4)
84h
(4)
85h
86h
87h
88h
(5)
89h
(5)
8Ah
(1,4)
8Bh
(4)
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
20, 44, 96
PCL
Program Counter (PC) Least Significant Byte
0000 0000
26, 96
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
(2)
0001 1xxx
19, 96
FSR
Indirect data memory address pointer
xxxx xxxx
27, 96
TRISA
TRISB
TRISC
—
—
PORTA Data Direction Register
--11 1111
32, 96
34, 96
35, 96
PORTB Data Direction Register
PORTC Data Direction Register
1111 1111
1111 1111
TRISD
PORTD Data Direction Register
1111 1111
36, 96
TRISE
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
0000 -111
38, 96
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
26, 96
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
8Ch
PIE1
PSPIE
(3)
—
—
Unimplemented
Unimplemented
Unimplemented
Timer2 Module Period Register
Synchronous Serial Port (I
2
C mode) Address Register
SMP
CKE
D/A
Unimplemented
Unimplemented
Unimplemented
CSRC
TX9
TXEN
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
x
= unknown,
u
= unchanged,
q
= value depends on condition, – = unimplemented, read as ‘
0
’, r = reserved.
Shaded locations are unimplemented, read as ‘
0
’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (
CALL
or
GOTO
).
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘
0
’.
This bit always reads as a ‘
1
’.
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
22, 97
8Dh
8Eh
8Fh
90h
91h
92h
PIE2
PCON
—
—
—
PR2
—
—
—
—
—
—
—
—
—
—
—
CCP2IE
BOR
---- ---0
24, 97
22, 97
—
—
—
52, 97
POR
---- --qq
—
—
—
1111 1111
93h
SSPADD
0000 0000
68, 97
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
SSPSTAT
—
—
—
TXSTA
SPBRG
—
—
—
—
—
ADCON1
P
S
R/W
UA
BF
0000 0000
—
—
—
60, 97
—
—
—
69, 97
71, 97
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
—
—
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
84, 97
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Details
on page
Note
1:
2:
3:
4:
5:
6:
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