Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
592
Upon detecting 3 consecutive PRBS byte errors, the monitor will enter the Out of
Synchronization State and automatically try to resynchronize to the incoming PRBS stream.
Once synchronized to the incoming stream, it will take 4 consecutive non-erred PRBS bytes to
change back into the Synchronized State. The auto synchronization is useful when the input
frame alignment of the monitored stream changes. The realignment will affect the PRBS
sequence causing all input PRBS bytes to mismatch and forcing the need for a resynchronization
of the monitor. The auto resynchronization does this, detecting a burst of errors and
automatically re-synchronizing.
14.22.3 Master/Slave Configuration for STS-48c/STM-16c Payloads
To monitor STS-48c/STM-16c payloads, a master/slave configuration is available where each
monitor receives 1/4 of the concatenated stream. In the case of a STS-48c/STM-16c, 4 PRGMs
are used in a master/slave configuration. Because the payload is four bytes interleaved, after a
group of four consecutive bytes, a jump in the sequence takes place. The number of bytes that
must be skipped can be determined using the number of PRGMs in the master/slave
configuration. For example, to process an STS-48c/STM-16c, the number of sequence to skip is
(4 PRGMS * 4 bytes) – 3 = 13. So, 13 sequences will be skipped after each group of four
consecutive bytes.
The PRBS monitor can be re-initialize by the user by writing in a normal register of the master
PRGM. Since all the slave PRGMs use the LFSR state of the previous PRGM in the chain, they
will be re-initialize too.
14.22.4 Special Note for Use of PRGM in STS-48c/STM-16c mode (TX48C = 1 or
RX48C = 1)
The PRGMs always expect and generate data in the format shown in Table 52. For standard line-
side STS-48c/STM-16c timeslot mappings, the IWTI_MODE[1:0], IPTI_MODE[1:0],
OWTI_MODE[1:0], or OPTI_MODE[1:0] bits in the S/UNI-MACH48 Miscellaneous register
can be set to ‘b00 to automatically provide the proper mapping to the PRGM for PRBS detection.
Because the system-side timeslot map that the master/slave configuration of the PRGMs in STS-
48c/STM-16c mode is different than that required by the other blocks, the xxTI_MODE[1:0] bits
previously mentioned may have to be altered. This may cause the other blocks to receive data in
corrupted format, but they should not be in use in any case because the PRBS data stream from/to
the PRGM block will not contain packet or ATM data that can be processed by the downstream
S/UNI-MACH48 blocks.