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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
9
14.17.1
RXPHY POS-PHY L3 Servicing Algorithm ........................................584
14.18
Setting ATM Mode of Operation over Utopia L3 or POS-PHY L3 ..................586
14.18.1
Transmit UL3 Interface Misalignment Recovery................................587
14.18.2
Receive UL3 Interface Misalignment Recovery.................................587
14.19
Setting Packet Mode of Operation Over POS-PHY L3 ..................................587
14.20
Setting Transparent Mode of Operation Over POS-PHY L3 ..........................588
14.21
SIRP Configuration Options............................................................................588
14.21.1
SIRP Concatenated Channel Configuration......................................588
14.21.2
SIRP Modes of Operation..................................................................590
14.22
PRBS Generator and Monitor (PRGM) ..........................................................590
14.22.1
Mixed Payload (STS-12c, STS-3c, and STS-1) ................................591
14.22.2
Synchronization .................................................................................591
14.22.3
Master/Slave Configuration for STS-48c/STM-16c Payloads............592
14.22.4
Special Note for Use of PRGM in STS-48c/STM-16c mode (TX48C = 1 or
RX48C = 1)........................................................................................592
14.22.5
Error Detection and Accumulation.....................................................593
14.22.6
B1/E1 Overwrite and Detection .........................................................593
14.23
DS3 PRBS and Repetitive Pattern Generation with PRGD ...........................594
14.23.1
Generating and Detecting Repetitive Patterns ..................................594
14.23.2
Common Test Patterns ......................................................................595
14.24
Interrupt Service Routine................................................................................596
14.25
Accessing Indirect Registers..........................................................................597
14.26
Using the Performance Monitoring Features..................................................598
14.27
Using the Internal DS3 FDL Transmitter.........................................................598
14.28
Using the Internal DS3 FDL Receiver ............................................................601
14.29
Transmitting Bit Oriented Codes.....................................................................605
14.30
Loopback Operation .......................................................................................605
14.31
JTAG Support .................................................................................................606
14.31.1
TAP Controller....................................................................................608
14.31.2
States.................................................................................................610
14.31.3
Boundary Scan Instructions............................................................... 611
14.32
Power Up Sequence....................................................................................... 611
14.33
Reset Sequence.............................................................................................612
14.34
Clock Glitch Recovery ....................................................................................612
14.35
LVDS Analog Power Filtering..........................................................................612