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Multi-Service Access Device For Channelized Interfaces
Telecom Standard Product Data Sheet
Production
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990823, Issue 4
598
14.26 Using the Performance Monitoring Features
The performance monitor counters within the different blocks are provided for performance
monitoring purposes. The DS3 PMON, PLCP PMON, TCFP, RCFP, TTDP, RTDP, R8TD,
RXSDQ, TXSDQ, PRGD, and PRGM all contain performance monitor registers. The counters
have been sized to not saturate if polled every second.
Depending on the block, its counters can be accumulated independently in one of two ways: one
of the registers which contain the latched counter values is written to or if its 'transfer trigger'
register is written to. A device update of all the counters can be done by writing to the S/UNI-
MACH48 Global Performance Monitor Update register (register 0000H). After this register is
written to, the TIP bit in this register can be polled to determine when all the counter values have
been transferred and are ready to be read.
14.27 Using the Internal DS3 FDL Transmitter
It is important to note that the access rate to the TDPR registers is limited by the rate of the high-
speed system clock. Consecutive accesses to each TDPR Configuration, TDPR Interrupt
Status/UDR Clear, and TDPR Transmit Data register should be accessed (with respect to WRB
rising edge and RDB falling edge) at a rate no faster than 1/32 that of SYSCLK. This time is
used by the high-speed system clock to sample the event, write the FIFO, and update the FIFO
status. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the
line clock) must be considered when determining the procedure used to read and write the TDPR
registers.
Upon reset of the S/UNI-MACH48, the TDPR should be disabled by setting the EN bit in the
TDPR Configuration Register to logic 0 (default value). An HDLC all-ones Idle signal will be
sent while in this state. The TDPR is enabled by setting the EN bit to logic 1. The FIFOCLR bit
should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit.
To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS
generation is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt
driven mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and
LFILLE bits in the TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in
the TDPR Upper Transmit Threshold and TDPR Lower Interrupt Threshold registers should be
set to the desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR
automatically begins the transmission of HDLC packets, even if no complete packets are in the
FIFO. Transmission will continue until current packet is transmitted and the number of bytes in
the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all
complete HDLC packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be
enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1,
continuous flags will be sent.