- 您現在的位置：買賣IC網 > PDF目錄370021 > PSD813F3V 60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a UB Surface Mount package; Similar to IRHLUB7970Z4 with optional Total Dose Rating of 300kRads PDF資料下載
參數資料
| 型號： | PSD813F3V |
| 英文描述： | 60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a UB Surface Mount package; Similar to IRHLUB7970Z4 with optional Total Dose Rating of 300kRads |
| 中文描述： | Flash在系統(tǒng)編程（ISP）外設的8位微控制器 |
| 文件頁數： | 18/103頁 |
| 文件大?。?/td> | 1185K |
| 代理商： | PSD813F3V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁
PSD81XFX, PSD83XF2, PSD85XF2
18/103
DETAILED OPERATION
As shown in Figure 3, the PSD8XXFX consists of
six major types of functional blocks:
I
Memory Blocks
I
PLD Blocks
I
MCU Bus Interface
I
I/O Ports
I
Power Management Unit (PMU)
I
JTAG Interface
The functions of each block are described in the
following sections. Many of the blocks perform
multiple functions, and are user configurable.
MEMORY BLOCKS
The PSD8XXFX has the following memory blocks:
– Primary Flash memory
– Optional Secondary Flash memory
– Optional SRAM
The Memory Select signals for these blocks origi-
nate from the Decode PLD (DPLD) and are user-
defined in PSDsoft Express.
Primary Flash Memory and Secondary Flash
memory Description
The primary Flash memory is divided evenly into
eight equal sectors. The secondary Flash memory
is divided into four equal sectors. Each sector of
either memory block can be separately protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis. Flash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy (PC3).
This pin is set up using PSDsoft Express Configu-
ration.
Memory Block Select Signals
The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
“PLDS”, on page 30). Each of the eight sectors of
the primary Flash memory has a Select signal
(FS0-FS7) which can contain up to three product
terms. Each of the four sectors of the secondary
Flash memory has a Select signal (CSBOOT0-
CSBOOT3) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector to be mapped in differ-
ent areas of system memory. When using a MCU
with separate Program and Data space, these
flexible Select signals allow dynamic re-mapping
of sectors from one memory space to the other.
Ready/Busy (PC3).
This signal can be used to
output the Ready/Busy status of the PSD8XXFX.
The output on Ready/Busy (PC3) is a 0 (Busy)
when Flash memory is being written to, or
when
Flash memory is being erased. The output is a 1
(Ready) when no WRITE or Erase cycle is in
progress.
Memory Operation.
The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus Interface. The MCU can ac-
cess these memories in one of two ways:
I
The MCU can execute a typical bus WRITE or
READ operation
just as it would if accessing a
RAM or ROM device using standard bus cycles.
I
The MCU can execute a specific instruction
that
consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to invoke an embedded algorithm.
These instructions are summarized in Table 8.
Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de-
vice. However, Flash memory can only be altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as it would write a byte to
RAM. To program a byte into Flash memory, the
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a READ operation or polling
Ready/Busy (PC3).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
相關PDF資料 |
PDF描述 |
|---|---|
| PSD813F4V | -200V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA597260 with Standard Packaging |
| PSD813F5V | -60V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA9064 with optional Total Dose Rating of 300kRads |
| PSD86 | THREE PHASE RECTIFIER BRIDGE |
| PSF101 | WORLD MAGNETICS ULTRA SENSITIVEPRESSURESWITCHES |
| PSG61 | 4 KEY BI-BI CALL |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PSD813F3V-12 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V |
| PSD813F3V-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F3V-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F3V-12JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD813F3V-12JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發(fā)布緊急采購，3分鐘左右您將得到回復。