參數(shù)資料
型號(hào)： Q67107-H5167-A703
廠商： SIEMENS AG
英文描述： DDC-PLUS-Deflection Controller
中文描述： DDC的加偏轉(zhuǎn)控制器
文件頁(yè)數(shù)： 12/47頁(yè)
文件大?。?/td> 237K
代理商： Q67107-H5167-A703
SDA 9361
Semiconductor Group
12
1998-02-01
2.2
The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase
locked to the incoming horizontal sync pulse and exactly 864 times faster then the
horizontal frequency. In order to lock the internal frequency to the external sync signal
positive horizontal sync pulses are required (
see figure 4
).
Circuit Description
Figure 4
Incoming Signal HSYNC (CLEXT = 0)
Pulse width
t
w
for
Ι
2
C-Bus Bit ’HSWID’ = 0:
3
μ
s ... 6.1
μ
s
1.5
μ
s ... 3.1
μ
s
Pulse width
t
w
for
Ι
2
C-Bus Bit ’HSWID’ = 1:
3
μ
s ... 8.8
μ
s
1.5
μ
s ... 4.0
μ
s
Rise time
t
r
:100 ns minimum (CLEXT = 0)
low FH-range
high FH-range
low FH-range
high FH-range
The described input signal is first applied to an A/D converter. Conversion takes place
with 6 Bits and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to
obtain defined slopes for further measurements (PAL/NTSC applications). In addition
the actual high and low level of the signal as well as a threshold value is evaluated and
used to calculate the phase error between internal clock and external horizontal sync
UED10279
r
t
HSmax
V
HSmin
V
V
HSpp
W
t
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