參數(shù)資料
型號： Q67107-H5167-A703
廠商： SIEMENS AG
英文描述： DDC-PLUS-Deflection Controller
中文描述： DDC的加偏轉控制器
文件頁數(shù)： 13/47頁
文件大?。?/td> 237K
代理商： Q67107-H5167-A703
SDA 9361
Semiconductor Group
13
1998-02-01
pulse. By means of digital PI filtering an increment is gained from this. The PI filter can
be set by the
Ι
2
C-Bus VCR bit so that the lock-in behavior of the PLL is optimal in relation
to either the TV or VCR mode. Moreover it is possible to adapt the nominal frequency by
means of 5
Ι
2
C-Bus bits (INCR4..INCR0) to different horizontal frequencies. An
additional bus bit GENMOD offers the possibility to use the PLL as a frequency
generator which frequency is controlled by the INCR bits.
Once an increment has been obtained, either from the PI-filter or the
Ι
2
C Bus, it can be
used to operate the Digital Timing Oscillator. The DTO generates a saw-tooth with a
frequency that is proportional to the increment. The saw-tooth is converted into a
sinusoidal clock signal by means of sin ROM’s and D/A converters and applied to an
analog PLL which multiplies the frequency by 2 or 4 (depends on mode 1F
H
or 2F
H
; for
detailed explanation see pinning and
Ι
2
C-Bus description) and minimizes residual jitter.
In this manner the required line locked clock is provided to operate the other functional
parts of the circuit. If no HSYNC is applied to pin 35 the system holds its momentary
frequency for 2040 lines and following resets the PLL to its nominal frequency. The
status bit CON indicates the lock state of the PLL.
The system also provides a stable HS-pulse for internal use. The phase between this
internal pulse and the external HSYNC is adjustable via
Ι
2
C-Bus bits HPHASE. It can be
shifted over the range of one TV line.
An external clock (CLKI) can be provided by pin selection (CLEXT = H). The clock
frequency has to be 864
*
f
HSYNC
.
The external clock mode can not be used with
33.75 kHz and 35 kHz line frequency.
For effective noise suppression the VSYNC has to pass a window at first and is then
processed in a flywheel logic. The window allows a VSYNC pulse only after a minimum
number of lines from its predecessor and sets an artificial one after a maximum number
of lines. The number of H-periods between two subsequent VSYNCs is stored and
determines (after several checks) the following V-periods (internal synchronization). If
incoincidence is detected between internal and external VSYNC, the system switches
after a hysteresis of a defined number of V-periods to external synchronization and the
checks are repeated.
Values which influence shape and amplitude of the output signals are transmitted as
reduced binary values to the SDA 9361 via
Ι
2
C Bus. A CPU which is designed for speed
reasons in a pipe line structure calculates in consideration of feedback signals (e.g.ABL)
values which exactly represent the output signals. These values control after D/A
conversion the external deflection and raster correction circuits.
The CPU firmware is stored in an internal ROM.
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