參數(shù)資料
型號(hào): Q67107-H5167-A703
廠商: SIEMENS AG
英文描述: DDC-PLUS-Deflection Controller
中文描述: DDC的加偏轉(zhuǎn)控制器
文件頁(yè)數(shù): 19/47頁(yè)
文件大?。?/td> 237K
代理商: Q67107-H5167-A703
SDA 9361
Semiconductor Group
19
1998-02-01
STDBY:
Stand-by mode
0:
normal operation
1:
stand-by mode (all internal clocks are disabled)
2FH:
Setting of line frequency
0:
low range of line frequency (14900 Hz ... 17650 Hz)
1:
high range of line frequency (29800 Hz ... 35300 Hz)
N
ote:
this bit is don’t care if pin SELFH1_2 has L-level
BD:
Blanking disable
0:
horizontal and vertical blanking enabled
1:
horizontal and vertical blanking disabled
RABL:
ABL input range
0:
2 V ... 3 V
1:
0 V ... 4 V
VR1 ... VR0:
Reduction of the vertical size
00: 100 % V-size
01: 75 % V-size
10: 66 % V-size
11: 50 % V-size
(16:9 source on 16:9 display)
(16:9 source on 4:3 display)
(two 4:3 sources on 16:9 display)
(two 16:9 sources on 16:9 display)
HDE:
HD enable
0:
1:
Default value depends on pin 40 (SSD)
SSD = Low: 0
SSD = High: 1
line is switched off (HD disabled, that is L-level)
line is switched on (HD enabled)
The
Deflection Control Byte 1
includes the following bits:
NSA:
No self adaptation
0:
self adaptation on
1:
self adaptation off
0
X
NSA
STE
GBE
SRSE
SSE
BSE
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