參數(shù)資料
型號(hào): Q67107-H5167-A703
廠商: SIEMENS AG
英文描述: DDC-PLUS-Deflection Controller
中文描述: DDC的加偏轉(zhuǎn)控制器
文件頁數(shù): 8/47頁
文件大?。?/td> 237K
代理商: Q67107-H5167-A703
SDA 9361
Semiconductor Group
8
1998-02-01
1.4
Pin Description
(cont’d)
1)
The external clock mode can not be used with 33.75 kHz and 35 kHz line frequency.
Pin No. Symbol
28
29
30
Type
I/TTL
Q
I/TTL
Description
V-sync input
Control signal output for H driver stage
Switching normal operation (TEST = L) and test mode
(TEST = H: pins 7, 27, 31, 32, 33, 40, 44 are additional
test pins)
Switching between 1F
H
mode (L) and 2F
H
mode (H)
(Pin SELFH1_2 = 0)
Switching between internal (L) and external clock (H)
1)
Selection of switching between 1F
H
mode and 2F
H
mode
SELFH1_2 = 0:1F
H
/2F
H
selected via pin FH1_2
SELFH1_2 = 1:1F
H
/2F
H
selected via
Ι
2
C-Bus register 00
H
, Bit D5
Analog supply
HSYNC input (CLEXT = 1: TTL; CLEXT = 0: analog)
1)
Reference voltage for sync ADC
Analog ground
Digital supply
Digital ground
Disables softstart
Analog ground
PLL loop filter
Analog supply
Defines default value of VOFF-Bit
(
Ι
2
C-Bus register 00
H
, Bit D7)
VSYNC
HD
TEST
31
FH1_2
I/TTL
32
33
CLEXT
SELFH1_2 I/TTL
I/TTL
34
35
36
37
38
39
40
41
42
43
44
V
DD(A3)
HSYNC
V
REFC
V
SS(A3)
V
DD(D)
V
SS(D)
SSD
V
SS(A4)
LF
V
DD(A4)
VOFFD
S
I
I
S
S
S
I/TTL
S
IQ
S
I/TTL
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