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參數(shù)資料
| 型號(hào)： | Q67107-H5167-A703 |
| 廠商： | SIEMENS AG |
| 英文描述： | DDC-PLUS-Deflection Controller |
| 中文描述： | DDC的加偏轉(zhuǎn)控制器 |
| 文件頁(yè)數(shù)： | 23/47頁(yè) |
| 文件大小： | 237K |
| 代理商： | Q67107-H5167-A703 |
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SDA 9361
Semiconductor Group
23
1998-02-01
The
Universal Register 1 (Subaddress 45
H
)
includes the following bit:
NOISYVCR:
Handling of noisy input signals in VCR mode
0:
normal handling
1:
improved handling
Note:
this bit is don’t care if bit VCR = 0 (TV mode)
The
Universal Register 3 (Subaddress 47
H
)
includes the following bits:
KILL_ZIP:
Top flutter suppression
0:
no top flutter suppression
1:
top flutter suppression
(phase jumps max.
±
12
μ
s for low FH-range
rsp. max.
±
6
μ
s for high FH-range)
TC_3RD:
Third time constant
0:
slow VCR time constant
1:
fast VCR time constant
Note:
this bit is don’t care if bit VCR = 0 (TV mode)
The
Internal Voltage Ref. Control Byte
includes the following bits:
BANDG4 ...
BANDG0:
Adjustment of internal bandgap reference
10000: Reference Output voltage min
:
01111: Reference Output voltage max
Typical adjustment range is 0.5 V.
BANDGOFF: Bandgap Off
0:
V
REFH
,
V
REFL
derived internally from
V
REFP
0
0
NOISY
VCR
0
0
0
0
0
0
0
0
KILL_ZIP TC_3RD
0
0
0
BANDG4 BANDG3 BANDG2 BANDG1 BANDG0
BANDG
OFF
BANDG4
OFF
0
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