參數(shù)資料
型號(hào): Q67107-H5167-A703
廠商: SIEMENS AG
英文描述: DDC-PLUS-Deflection Controller
中文描述: DDC的加偏轉(zhuǎn)控制器
文件頁(yè)數(shù): 21/47頁(yè)
文件大小: 237K
代理商: Q67107-H5167-A703
SDA 9361
Semiconductor Group
21
1998-02-01
NL2 ... NL0:
Number of lines per field when NR = 1 and no vertical sync
at the input is detected
The
Internal PLL Control Byte
includes the following bits:
HSWID:
Maximum width of HSYNC
0:
6.1
μ
s
3.1
μ
s
1:
8.8
μ
s
4.0
μ
s
for low FH-range
for high FH-range
for low FH-range
for high FH-range
GENMOD:
Clock generator mode
0:
normal PLL mode
1:
generator mode (fixed frequency output, controlled by INCR..)
VCR:
PLL filter optimized for
0:
TV mode
1:
VCR mode
INCR4 ... 0:
Nominal PLL output frequency
for low FH-range:
INCR = INT((FH
*
110592) / FQ - 64.625)
for high FH-range:
INCR = INT((FH
*
55296) / FQ - 64.625)
(for typical values see table below)
NL2
NL1
NL0
Number of Lines per Field
0
0
0
262.5
0
0
1
312.5
0
1
0
525
0
1
1
562.5
1
X
X
625
HSWID
GENMOD
VCR
INCR4
INCR3
INCR2
INCR1
INCR0
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