參數(shù)資料
型號: RC28F128P33T85
廠商: NUMONYX
元件分類: PROM
英文描述: 8M X 16 FLASH 3V PROM, 85 ns, PBGA64
封裝: BGA-64
文件頁數(shù): 26/96頁
文件大?。?/td> 1378K
代理商: RC28F128P33T85
Numonyx StrataFlash Embedded Memory (P33)
Datasheet
November 2007
32
Order Number: 314749-05
Synchronous Specifications(5,6)
R301
tAVCH/L
Address setup to CLK
9
-
ns
1
R302
tVLCH/L
ADV# low setup to CLK
9
-
ns
R303
tELCH/L
CE# low setup to CLK
9
-
ns
R304
tCHQV / tCLQV CLK to output valid
-
17
ns
R305
tCHQX
Output hold from CLK
3
-
ns
1,7
R306
tCHAX
Address hold from CLK
10
-
ns
1,4,7
R307
tCHTV
CLK to WAIT valid
-
17
ns
1,7
R311
tCHVL
CLK Valid to ADV# Setup
3
-
ns
1
R312
tCHTX
WAIT Hold from CLK
3
-
ns
1,7
Notes:
1.
See
max allowable input slew rate.
2.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3.
Sampled, not 100% tested.
4.
Address hold in synchronous burst read mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5.
Please see the latest P33 Spec Update for synchronous busrt operation on TSOP packages.
6.
Synchronous burst read mode is not supported with TTL level inputs.
7.
Applies only to subsequent synchronous reads.
Table 17: AC Read Specifications - 130nm (Sheet 3 of 3)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Table 18: AC Read Specification differences for 65nm
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
R1
tAVAV
Read cycle time
95
-ns
2
TSOP
105
ns
2
R2
tAVQV
Address to output valid
-
95
ns
2
TSOP
105
ns
2
R3
tELQV
CE# low to output valid
-
95
ns
2
TSOP
105
ns
2
R103
tVLQV
ADV# low to output valid
-
95
ns
1,2
TSOP
105
ns
2
Notes:
1.
See
max allowable input slew rate.
2.
This is the recommended specification for all new designs supporting both 130nm and 65nm lithos, or for new designs
that will use the 65nm lithography. All other timings not listed here remain the same as referenced by
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