參數(shù)資料
型號(hào)： RC28F128P33T85
廠商： NUMONYX
元件分類： PROM
英文描述： 8M X 16 FLASH 3V PROM, 85 ns, PBGA64
封裝： BGA-64
文件頁(yè)數(shù)： 36/96頁(yè)
文件大?。?/td> 1378K
代理商： RC28F128P33T85
November 2007
Datasheet
Order Number: 314749-05
41
Numonyx StrataFlash Embedded Memory (P33)
8.0
Power and Reset Specifications
8.1
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
8.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 21: Power and Reset
Num
Symbol
Parameter
Min
Max
Unit
Notes
P1
tPLPH
RST# pulse width low
100
-
ns
1,2,3,4
P2
tPLRH
RST# low to device reset during erase
-
25
s
1,3,4,7
RST# low to device reset during program
-
25
1,3,4,7
P3
tVCCPH
VCC Power valid to RST# de-assertion (high)
130nm
90
-
1,4,5,6
VCC Power valid to RST# de-assertion (high)
65nm
300
-
Notes:
1.
These specifications are valid for all device versions (packages and speeds).
2.
The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
3.
Not applicable if RST# is tied to Vcc.
4.
Sampled, but not 100% tested.
5.
When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.
6.
When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN..
7.
Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
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