參數(shù)資料
型號(hào): RIVA128
廠商: 意法半導(dǎo)體
英文描述: RIVA 128⑩ 128-BIT 3D MULTIMEDIA ACCELERATOR
中文描述: 麗娃128⑩128位3D多媒體加速器
文件頁(yè)數(shù): 23/85頁(yè)
文件大?。?/td> 609K
代理商: RIVA128
128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
23/85
5
PCI 2.1 LOCAL BUS INTERFACE
5.1
The RIVA128ZXsupports a glueless interface to PCI 2.1 with both master and slave capabilities. The host
interface is fully compliant with the 32-bit PCI 2.1 specification.
The Multimedia Accelerator supports PCI bus operation up to 33MHz with zero-wait state capability and
full bus mastering capability handling burst reads and burst writes.
Figure 16.
PCI interface pin connections
RIVA128ZX PCI INTERFACE
Table 5.
PCI bus commands supported by the RIVA128ZX
Bus master
Bus slave
Memory read and write
Memory read and write
Memory read line
I/O read and write
Memory read multiple
Configuration read and write
Memory read line
Memory read multiple
Memory write invalidate
P
PCICBE[3:0]#
PCIAD[31:0]
PCIFRAME#
PCIDEVSEL#
32
4
PCIIRDY#
PCITRDY#
PCISTOP#
PCIIDSEL
PCIREQ#
PCIGNT#
PCICLK
PCIRST#
PCIPAR
PCIINTA#
RIVA128ZX
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